Datasheet

AD9600
Rev. B | Page 57 of 72
06909-307
TEST TEST
TEST
TEST
VAL
CHANNELA
CHANNELB
DIGITAL/HSC-ADC-EVALCZ INTERFACE
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
74VCX162244MTD
U17
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
74VCX162244MTD
U16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
74VCX162244MTD
U15
SDI
CSB
SCLK
R145
RES040 2
0OHM
R142
RES040 2
0OHM
SDO
R141
RES040 2
0OHM
R119
RES040 2
0OHM
CSB_2
V_DIG
VS
R140
RES040 2
10KOHM
R118
RES040 2
10KOHM
R130R77
100OHM
SYNC
OUT6N
OUT6P
OUT6P
OUT6N
FD0B FD1B
DG10 DG9 DG8 DG7 DG6 DG5 DG4 DG3 DG2 DG1
A1 A2 A3 A4 A5 A6 A7 A8 A9
A10
B1 B2 B3 B4 B5 B6 B7 B8 B9
B10
C1 C2 C3 C4 C5 C6 C7 C8 C9
C10
D1 D2 D3 D4 D5 D6 D7 D8 D9
D10
BG10 BG9 BG8 BG7 BG6 BG5 BG4 BG3 BG2 BG1
TYCO_HM-ZD
J11
V_DIG
V_DIG
FD2B FD3B
SPARE1 SPARE2
V_DIG
V_DIG
V_DIG
V_DIG V_DIG DCOB DCOA
V_DIG
FD3A FD2A FD1A FD0A
V_DIG
PWR_SDO
PWR_SDFS
SCLK_OUT
SDFS_OUT SDO_OUT
PWR_SCLK
SDO_OUT
1
TP23
SCLK_OUT
SDFS_OUT
1
TP21
V_DIG
C65 0.1U
VS
C71 0.1U
C70 0.1U
C69 0.1U
C68 0.1U
C66 0.1U
C67 0.1U
C72 0.1U
C73 0.1U
C76 0.1U
C74 0.1U
C75 0.1U
RESETB
DG10 DG9 DG8 DG7 DG6 DG5 DG4 DG3 DG2 DG1
A1 A2 A3 A4 A5 A6 A7 A8 A9
A10
B1 B2 B3 B4 B5 B6 B7 B8 B9
B10
C1 C2 C3 C4 C5 C6 C7 C8 C9
C10
D1 D2 D3 D4 D5 D6 D7 D8 D9
D10
BG10 BG9 BG8 BG
7
BG
6
BG5 BG4 BG3 BG2 BG1
TYCO_HM-ZD
J12
DG10 DG9 DG8 DG7 DG6 DG5 DG4 DG3 DG2 DG1
A1 A2 A3 A4 A5 A6 A7 A8 A9
A10
B1 B2 B3 B4 B5 B6 B7 B8 B9
B10
C1 C2 C3 C4 C5 C6 C7 C8 C9
C10
D1 D2 D3 D4 D5 D6 D7 D8 D9
D10
BG10 BG9 BG8 BG7 BG6 BG5 BG4 BG3 BG2 BG1
TYCO_HM-ZD
J10
1
TP22
1
TP24
V_DIG
R143
RES040 2
0OHM
R144
RES040 2
0OHM
SPARE3 SPARE4
D0B D1B D2B D3B
D4B D5B D6B D7B D8B D9B
SPARE5 SPARE6
SPARE8 SPARE7
D0A D1A D2A D3A
D4A D5A D6A D7A D8A D9A
Figure 80. Evaluation Board Schematic, Digital Output Interface