Datasheet

AD9600
Rev. B | Page 54 of 72
06909-304
TEST
TEST
TEST
BYPASS_LDO CLK CP
CP_RSET
GND_ESD
GND_OUT89_DIV
GND_REF
LD LF NC1
NC2
NC3
NC4
OUT0
OUT1
OUT2 OUT3
OUT4
OUT5
OUT6 OUT7 OUT8 OUT9
REFIN
REFMON REF_SEL
RSET_CLOCK
SCLK
SDIO
SDO
STATUS VCP VS_CLK_DIST
VS_OUT01_DIV
VS_OUT01_DRV
VS_OUT23_DIV
VS_OUT23_DRV
VS_OUT45_DIV
VS_OUT45_DRV
VS_OUT67_1
VS_OUT67_2
VS_OUT89_1
VS_OUT89_2
VS_PLL_1
VS_PLL_2
VS_PRESCALER
VS_REF
VS_VCO CLKB
CSB
OUT0B
OUT1B
OUT2B OUT3B
OUT4B
OUT5B
OUT6B OUT7B OUT8B OUT9B
PDB
REFINB
RESETB
SYNCB
AD9516_64LFCSP
PAD
2
AD9516 CLK IN
LVDS
OUTPUT
LVPECL OUTPU
T
TO ADC LVPECL
1
S7
VCXO_CLK -
R89
49.9OHM
R12
4.12 K
R9
100OHM
R75
100OHM
1
TP8
2
1
S11
OUT6P OUT6N
10 13
5
62
44 37
59
3 9
15
18
19
20
56
53
43 40
25
28
48 46 33 35
2 7
58
22
21
6 4
12
51
54
38 41
30
27
49
5031
32
61
60
57
11 14
17
55
52
42 39
26
29
47 45 34 36
24
63
23
8 1
16
64
U2
200 R91
200 R86
R11
5.1K
200 R88
200 R92R125
RES040 2
0OHM
R124
RES040 2
0OHM
R10
0OHM
C104 0.1U
C101 0.1U
C98 0.1U
C99 0.1U
C96 0.1U
C97 0.1U
C100 0.1U
SYNC
VCP
VS_OUT_DR
VCXO_CLK +
1
TP18
LD
1
TP19
C80 18PF
C141
0.001U
C86
0.1U
C85
0.1U
C87
0.1U
C88
0.1U
C143
0.1U
C142
0.1U
2
1
S10
2
1
S9
2
1
S8
1
TP20
OPT_CLK+
SCLK
VS
SYNCB
RESETB
OPT_CLK-
PDB
CSB_2
VS
VS
VS
VS
VS
VS_OUT_DR
VS_OUT_DR
VS
VS_OUT_DR
VCP
SDO
SDI
REF_SEL
LF
AGND
AGND
AGNDCP
BYPASS_LDO
STATUS
REFMON
ALTCLK- ALTCLK+
Figure 77. Evaluation Board Schematic, Optional AD9516 Clock Circuit