Datasheet

AD9600
Rev. B | Page 5 of 72
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference,
DCS enabled, fast detect output pins disabled, signal monitor disabled, unless otherwise noted.
Table 1.
Parameter Temp
AD9600ABCPZ-105/
AD9600BCPZ-105
AD9600ABCPZ-125/
AD9600BCPZ-125
AD9600ABCPZ-150/
AD9600BCPZ-150
Min Typ Max Min Typ Max Min Typ Max Unit
RESOLUTION Full 10 10 10 Bits
ACCURACY
No Missing Codes Full Guaranteed Guaranteed Guaranteed
Offset Error Full ±0.3 ±0.7 ±0.3 ±0.7 ±0.3 ±0.7 % FSR
Gain Error Full −3.6 −2.2 −1.0 −4.0 −2.5 −1.3 −4.3 −3.0 −1.6 % FSR
Differential Nonlinearity (DNL)
1
Full ±0.2 ±0.2 ±0.2 LSB
25°C ±0.1 ±0.1 ±0.1 LSB
Integral Nonlinearity (INL)
1
Full ±0.3 ±0.3 ±0.4 LSB
25°C ±0.1 ±0.1 ±0.1 LSB
MATCHING CHARACTERISTICS
Offset Error Full ±0.3 ±0.7 ±0.3 ±0.7 ±0.2 ±0.7 % FSR
Gain Error Full ±0.2 ±0.8 ±0.3 ±0.8 ±0.2 ±0.8 % FSR
TEMPERATURE DRIFT
Offset Error Full ±15 ±15 ±15 ppm/°C
Gain Error Full ±95 ±95 ±95 ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode) Full ±5 ±16 ±5 ±16 ±5 ±16 mV
Load Regulation @ 1.0 mA Full 7 7 7 mV
INPUT-REFERRED NOISE
VREF = 1.0 V 25°C 0.1 0.1 0.1 LSB rms
ANALOG INPUT
Input Span, VREF = 1.0 V Full 2 2 2 V p-p
Input Capacitance
2
Full 8 8 8 pF
VREF INPUT RESISTANCE Full 6 6 6 kΩ
POWER SUPPLIES
Supply Voltage
AVDD, DVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
DRVDD (CMOS Mode) Full 1.7 3.3 3.6 1.7 3.3 3.6 1.7 3.3 3.6 V
Supply Current
I
AVDD
1
Full 310 385 419 mA
I
DVDD
1
Full 34 42 50 mA
I
AVDD
and I
DVDD
1, 3
365 455 495
I
DRVDD
(3.3 V CMOS) Full 35 36 42 mA
I
DRVDD
(1.8 V CMOS) Full 15 18 22 mA
I
DRVDD
(1.8 V LVDS) 42 44 46 mA
POWER CONSUMPTION
DC Input Full 600 650 750 800 825 890 mW
Sine Wave Input
1
DRVDD = 1.8 V Full 645 813 892 mW
DRVDD = 3.3 V Full 740 900 990 mW
Standby Power
3
Full 68 77 77 mW
Power-Down Power Full 2.5 6 2.5 6 2.5 6 mW
1
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
2
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 8 for the equivalent analog input structure.
3
Standby power is measured with a dc input and the CLK+ and CLK− pins inactive )set to AVDD or AGND.