Datasheet
AD9600
Rev. B | Page 39 of 72
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin,
and the SMI SCLK/PDWN pin serve as standalone CMOS-
compatible control pins. When the device is powered up, it is
assumed that the user intends to use the pins as static control
lines for the duty cycle stabilizer, output data format, output
enable, and power-down feature control. In this mode, the CSB
chip select should be connected to AVDD, which disables the
serial port interface.
Table 20. Mode Selection
Pin
External
Voltage Configuration
SDIO/DCS AVDD (default) Duty cycle stabilizer enabled
AGND Duty cycle stabilizer disabled
SCLK/DFS AVDD Twos complement enabled
AGND (default) Offset binary enabled
SMI SDO/OEB AVDD Outputs in high impedance
AGND (default) Outputs enabled
SMI SCLK/PDWN AVDD
Chip in power-down or
standby
AGND (default) Normal operation
SPI ACCESSIBLE FEATURES
Brief descriptions of the general features available on many
Analog Devices, Inc., high speed ADCs, including the AD9600,
that are accessible via the SPI are included in Table 21. These
feat
ures are described in detail in the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI. The AD9600 part-specific
features are described in the Memory Map Register Description
secti
o
n.
Table 21. Features Accessible Using the SPI
Feature Name Description
Modes
Allows the user to set either the power-down
mode or the standby mode
Clock Allows the user to access the DCS via the SPI
Offset
Allows the user to digitally adjust the
converter offset
Test I/O
Allows the user to set the test modes to have
known data on the output bits
Output Mode Allows the user to set up the outputs
Output Phase Allows the user to set the output clock polarity
Output Delay Allows the user to vary the DCO delay
VREF Allows the user to set the reference voltage
DON’T CARE
DON’T CAREDON’T CARE
DON’T CARE
SDIO
SCLK
CSB
t
S
t
DH
t
CLK
t
DS
t
H
R/W W1 W0 A12 A11 A10 A9 A8 A7
D5 D4 D3 D2 D1 D0
t
LOW
t
HIGH
06909-049
Figure 72. Serial Port Interface Timing Diagram