Datasheet

AD9600
Rev. B | Page 13 of 72
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
0
6909-002
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D1A D2A D3A
DRGND
DRVDD
D4A D5A
DVDD
D6A D7A D8A
(MSB) D9A
FD0A FD1A FD2A FD3A
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
DRGND D1B D0B (LSB) DNC DNC DNC DNC DVDD FD3B FD2B FD1B FD0B SYNC CSB CLK– CLK+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DRVDD
D2B
D3B
D4B
D5B
D6B
D7B
D8B
(MSB) D9B
DCOB
DCOA
DNC
DNC
DNC
DNC
(LSB) D0A
SCLK/DFS
SDIO/DCS
AVDD
AVDD
VIN + B
VIN – B
RBIAS
CML
SENSE
VREF
VIN – A
VIN + A
AVDD
SMI SDFS
SMI SCLK/PDWN
SMI SDO/OEB
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PIN 1
INDICATOR
AD9600
PARALLEL CMOS
TOP VIEW
(Not to Scale)
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE
ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO
GROUND FOR PROPER OPERATION.
Figure 6. Parallel CMOS Mode Pin Configuration (Top View)
Table 8. Parallel CMOS Mode Pin Function Descriptions
Pin No. Mnemonic Type Description
ADC Power Supplies
20, 64 DRGND Ground Digital Output Ground.
1, 21 DRVDD Supply Digital Output Driver Supply (1.8 V to 3.3 V).
24, 57 DVDD Supply Digital Power Supply (1.8 V Nominal).
36, 45, 46 AVDD Supply Analog Power Supply (1.8 V Nominal).
0 AGND Ground Analog Ground. Pin 0 is the exposed thermal pad on the bottom of the package.
ADC Inputs
37 VIN + A Input Differential Analog Input Pin (+) for Channel A.
38 VIN − A Input Differential Analog Input Pin (−) for Channel A.
44 VIN + B Input Differential Analog Input Pin (+) for Channel B.
43 VIN − B Input Differential Analog Input Pin (−) for Channel B.
39 VREF I/O Voltage Reference Input/Output.
40 SENSE Input Voltage Reference Mode Select (see Table 11 for details).
42 RBIAS Input External Reference Bias Resistor.
41 CML Output Common-Mode Level Bias Output for Analog Inputs.
49 CLK+ Input
ADC Master Clock True. The ADC clock can be driven using a single-ended
CMOS (see Figure 60 and Figure 61 for the recommended connection).
50 CLK− Input
ADC Master Clock Complement. The ADC clock can be driven using a single-
ended CMOS (see Figure 60 and Figure 61 for the recommended connection).