Datasheet

AD9600
Rev. B | Page 11 of 72
CLK+
DCO–
DCO+
CH A/CH B DATA
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
N + 8
N – 12 N – 11 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4
N – 13
CLK–
t
CLK
t
PD
t
CLK
t
A
CH A/CH B FAST
DETECT
ABABABABABABABABA AB
N – 10
N – 6 N – 5 N – 3 N – 2 N – 1 N N + 1 N + 2N – 7
ABABABABABABABABA AB
N – 4
t
DCO
06909-089
Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000)
SYNC
CLK+
t
HSYNC
t
SSYNC
06909-072
Figure 4. SYNC Input Timing Requirements
CLK+
S
MI SCLK/PDWN
SMI SDFS
DATA DATASMI SDO/OEB
CLK–
t
CSSCLK
t
SSCLKSDFS
t
SSCLKSDO
06909-082
Figure 5. Signal Monitor SPORT Output Timing (Divide-by-2 Mode)