Datasheet

ManualsBrandsANALOG DEVICES ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal LFCSP 64 VQ

10-Bit, 105 MSPS/125 MSPS/150 MSPS,

1.8 V Dual Analog-to-Digital Converter

AD9600

Rev. B

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

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Tel: 781.329.4700 www.analog.com

FEATURES

SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS

SFDR = 81 dBc to 70 MHz at 150 MSPS

Low power: 825 mW at 150 MSPS

1.8 V analog supply operation

1.8 V to 3.3 V CMOS output supply or 1.8 V LVDS supply

Integer 1 to 8 input clock divider

Intermediate frequency (IF) sampling frequencies up to 450 MHz

Internal analog-to-digital converter (ADC) voltage reference

Integrated ADC sample-and-hold inputs

Flexible analog input: 1 V p-p to 2 V p-p range

Differential analog inputs with 650 MHz bandwidth

ADC clock duty cycle stabilizer

95 dB channel isolation/crosstalk

Serial port control

User-configurable built-in self-test (BIST) capability

Energy-saving power-down modes

Integrated receive features

Fast detect/threshold bits

Composite signal monitor

APPLICATIONS

Point-to-point radio receivers (GPSK, QAM)

Diversity radio systems

I/Q demodulation systems

Smart antenna systems

Digital predistortion

General-purpose software radios

Broadband data applications

Data acquisition

Nondestructive testing

PRODUCT HIGHLIGHTS

1. Integrated dual, 10-bit, 150 MSPS/125 MSPS/105 MSPS ADC.

2. Fast overrange detect and signal monitor with serial output.

3. Signal monitor block with dedicated serial output mode.

4. Proprietary differential input maintains excellent SNR

performance for input frequencies up to 450 MHz.

5. The AD9600 operates from a single 1.8 V supply and

features a separate digital output driver supply to

accommodate 1.8 V to 3.3 V logic families.

6. A standard serial port interface supports various product

features and functions, such as data formatting (offset

binary, twos complement, or gray coding), enabling the

clock DCS, power-down mode, and voltage reference mode.

7. The AD9600 is pin compatible with the AD9627-11, AD9627,

and

AD9640

, allowing a simple migration from 10 bits to

11 b

its, 12 bits, or 14 bits.

FUNCTIONAL BLOCK DIAGRAM

6909-001

SIGNAL

MONITOR

SHA ADC

CMOS/LVDS

OUTPUT BUFFER

D9A

D0A

VIN + A

VIN – A

DRVDDDVDDAVDD CSB

SCLK/

DFS

SPI

PROGRAMMING DATA

SDIO/

DCS

FD[0:3]A

FD BITS/THRESHOLD

DETECT

SHA

ADC

CMOS/LVDS

OUTPUT BUFFER

D0B

D9B

VIN + B

VIN – B

DCOA

DCOB

CLK+

CLK–

DCO

GENERATION

DUTY CYCLE

STABLIZER

DIVIDE 1

TO 8

DRGNDSYNCAGND SMI

SDO/

OEB

SMI

SCLK/

PDWN

SERIAL MONITOR

DATA

SMI

SDFS

SERIAL MONITOR

INTERFACE

FD[0:3]B

FD BITS/THRESHOLD

DETECT

MULTICHIP

SYNC

VREF

SENSE

CML

–+

REFERENCE

SELECT

AD9600

NOTES

1.PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;

SEE FIGURE 7 FOR LVDS PIN NAMES.

Figure 1.

Summary of content (72 pages)

PAGE 1
0-Bit, 105 MSPS/125 MSPS/150 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9600 FEATURES I/Q demodulation systems Smart antenna systems Digital predistortion General-purpose software radios Broadband data applications Data acquisition Nondestructive testing SNR = 60.6 dBc (61.6 dBFS) to 70 MHz at 150 MSPS SFDR = 81 dBc to 70 MHz at 150 MSPS Low power: 825 mW at 150 MSPS 1.8 V analog supply operation 1.8 V to 3.3 V CMOS output supply or 1.
PAGE 2
AD9600 TABLE OF CONTENTS Features .............................................................................................. 1 Peak Detector Mode................................................................... 33 Applications ....................................................................................... 1 RMS/MS Magnitude Mode ....................................................... 33 Product Highlights ...........................................................................
PAGE 3
AD9600 REVISION HISTORY Added new models to Specifications Section ................................ 5 Changes to Table 7 ..........................................................................12 Updated Outline Dimensions ........................................................71 Changes to Ordering Guide ...........................................................72 Changes to Configuration Using the SPI Section ....................... 37 Changes to Table 22 .............................................
PAGE 4
AD9600 GENERAL DESCRIPTION The AD9600 is a dual, 10-bit, 105 MSPS/125 MSPS/150 MSPS ADC. It is designed to support communications applications where low cost, small size, and versatility are desired. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges.
PAGE 5
AD9600 SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, signal monitor disabled, unless otherwise noted. Table 1.
PAGE 6
AD9600 AC SPECIFICATIONS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, fast detect output pins disabled, signal monitor disabled, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.3 MHz fIN = 70 MHz fIN = 140 MHz fIN = 220 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 2.3 MHz fIN = 70 MHz fIN = 140 MHz fIN = 220 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.
PAGE 7
AD9600 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 3.
PAGE 8
AD9600 Parameter LOGIC INPUTS/OUTPUTS (SMI SDO/OEB, SMI SCLK/PDWN)2 High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = 3.3 V) Low Level Input Current Input Resistance Input Capacitance DIGITAL OUTPUTS CMOS Mode—DRVDD = 3.3 V High Level Output Voltage (IOH = 50 μA) High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Low Level Output Voltage (IOL = 50 μA) CMOS Mode—DRVDD = 1.
PAGE 9
AD9600 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 4.
PAGE 10
AD9600 TIMING CHARACTERISTICS Table 5. Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO Conditions Min Setup time between SYNC and the rising edge of CLK+ Hold time between SYNC and the rising edge of CLK+ SPORT TIMING REQUIREMENTS tCSSCLK tSSCLKSDO tSSCLKSDFS Delay from the rising edge of CLK+ to the rising edge of SMI SCLK Delay from the rising edge of SMI SCLK to SMI SDO Delay from the rising edge of SMI SCLK to SMI SDFS 10 ns 3.2 −0.
PAGE 11
AD9600 N+2 N+1 N+3 N N+4 N+8 tA N+5 N+6 N+7 tCLK CLK+ CLK– tPD CH A/CH B DATA A B A N – 12 N – 13 CH A/CH B FAST DETECT A B B A N–7 B N–6 A B N – 11 A B N–5 A B N – 10 A B N–4 A B A N–9 A B N–8 B A N–3 B N–2 tDCO A B N–7 A B N–1 A B A N–6 A B B N–5 A N B N+1 A N–4 A N+2 tCLK 06909-089 DCO+ DCO– Figure 3. LVDS Mode Data and Fast Detect Output Timing (Fast Detect Mode Select Bits = 000) CLK+ tHSYNC 06909-072 tSSYNC SYNC Figure 4.
PAGE 12
AD9600 ABSOLUTE MAXIMUM RATINGS Table 6.
PAGE 13
AD9600 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DRGND D1B D0B (LSB) DNC DNC DNC DNC DVDD FD3B FD2B FD1B FD0B SYNC CSB CLK– CLK+ PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD9600 PARALLEL CMOS TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCLK/DFS SDIO/DCS AVDD AVDD VIN + B VIN – B RBIAS CML SENSE VREF VIN – A VIN + A AVDD SMI SDFS SMI SCLK/PDWN SMI SDO/OEB NOTES 1.
PAGE 14
AD9600 Pin No. ADC Fast Detect Outputs 29 30 31 32 53 54 55 56 Digital Inputs 52 Digital Outputs 16 to 19, 22, 23, 25 to 28 62, 63, 2 to 9 11 10 SPI Control 48 47 51 Signal Monitor Port 33 35 34 Do Not Connect 12 to 15, 58 to 61 Mnemonic Type Description FD0A FD1A FD2A FD3A FD0B FD1B FD2B FD3B Output Output Output Output Output Output Output Output Channel A Fast Detect Indicator (see Table 14 for details). Channel A Fast Detect Indicator (see Table 14 for details).
PAGE 15
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DRGND DNC DNC FD3+ FD3– FD2+ FD2– DVDD FD1+ FD1– FD0+ FD0– SYNC CSB CLK– CLK+ AD9600 PIN 1 INDICATOR 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) AD9600 PARALLEL LVDS TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCLK/DFS SDIO/DCS AVDD AVDD VIN + B VIN – B RBIAS CML SENSE VREF VIN – A VIN + A AVDD SMI SDFS SMI SCLK/PDWN SMI SDO/OEB NOTES 1. DNC = DO NOT CONNECT. 2.
PAGE 16
AD9600 Pin No. ADC Fast Detect Outputs 54 53 Mnemonic Type Description FD0+ FD0− Output Output 56 55 FD1+ FD1− Output Output 59 58 FD2+ FD2− Output Output 61 60 FD3+ FD3− Output Output Channel A/Channel B LVDS Fast Detect Indicator 0 True (see Table 14 for full details). Channel A/Channel B LVDS Fast Detect Indicator 0 Complement (see Table 14 for details). Channel A/Channel B LVDS Fast Detect Indicator 1 True (see Table 14 for details).
PAGE 17
AD9600 EQUIVALENT CIRCUITS DVDD 1kΩ SCLK/DFS 26kΩ 06909-004 06909-008 VIN Figure 12. Equivalent SCLK/DFS Input Circuit Figure 8. Analog Input Circuit AVDD 1kΩ SENSE 1.2V 10kΩ 10kΩ CLK+ 06909-005 06909-009 CLK– Figure 13. Equivalent SENSE Circuit Figure 9. Equivalent Clock Input Circuit DRVDD DVDD 26kΩ DVDD 1kΩ 06909-081 06909-010 CSB DRGND Figure 14. Equivalent CSB Input Circuit Figure 10. Digital Output DRVDD DVDD 26kΩ DVDD 1kΩ SDIO/DCS AVDD 06909-007 6kΩ Figure 11.
PAGE 18
AD9600 TYPICAL PERFORMANCE CHARACTERISTICS AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 3.3 V, sample rate = 150 MSPS, DCS enabled, 1 V internal reference, 2 V p-p differential input, VIN = −1.0 dBFS, 64k sample, and TA = 25°C, unless otherwise noted. 0 0 150MSPS 2.3MHz @ –1dBFS SNR = 60.6dB (61.6dBFS) ENOB = 9.9 BITS SFDR = 85.5dBc –20 AMPLITUDE (dBFS) –40 –60 SECOND HARMONIC THIRD HARMONIC –80 20 30 40 50 60 70 0 10 20 30 40 50 FREQUENCY (MHz) 60 70 Figure 19.
PAGE 19
AD9600 0 0 150MSPS 440MHz @ –1dBFS SNR = 60.0dB (61.0dBFS) ENOB = 9.6 BITS SFDR = 70.0dBc –20 AMPLITUDE (dBFS) –40 SECOND HARMONIC –60 THIRD HARMONIC –80 THIRD HARMONIC SECOND HARMONIC –80 10 20 30 40 50 FREQUENCY (MHz) 60 70 –120 0 Figure 22. AD9600-150 Single-Tone FFT with fIN = 440 MHz 10 20 30 40 FREQUENCY (MHz) 50 60 06909-125 0 06909-122 –120 Figure 25. AD9600-125 Single-Tone FFT with fIN = 70.1 MHz 0 0 125MSPS 2.3MHz @ –1dBFS SNR = 60.6dB (61.6dBFS) ENOB = 9.
PAGE 20
AD9600 95 120 90 SFDR +25°C SFDR (dBFS) SNR (dBFS) SFDR –40°C 85 80 SNR/SFDR (dBc) SNR/SFDR (dBc AND dBm) 100 60 85dB REFERENCE LINE 40 80 75 SFDR +85°C 70 SNR +25°C SNR +85°C SNR –40°C 65 SFDR (dBc) 20 60 –40 –30 –20 –10 0 AMPLITUDE (dBm) 55 Figure 28. AD9600-150 Single-Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN = 2.4 MHz 0 50 100 150 200 250 350 400 –2.5 0.5 SFDR (dBFS) 80 GAIN –3.0 GAIN ERROR (%FSR) SNR (dBFS) 60 85dB REFERENCE LINE 40 450 Figure 31.
PAGE 21
AD9600 0 0 150MSPS 169.1MHz @ –7dBFS 172.1MHz @ –7dBFS SFDR = 83.1dBc (90.1dBFS) SFDR (dBc) –20 AMPLITUDE (dBFS) –40 IMD3 (dBc) –60 SFDR (dBFS) –80 –60 –80 IMD3 (dBFS) –100 –100 –36 –24 INPUT AMPLITUDE (dBFS) –12 –120 Figure 34. AD9600-150 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz, fS = 150 MSPS 0 20 30 40 50 INPUT FREQUENCY (MHz) 60 70 Figure 37. AD9600-150 Two-Tone SFDR/IMD3 vs. Input Frequency (fIN) with fIN1 = 169.1 MHz, fIN2 = 172.
PAGE 22
AD9600 12 100 0.10 LSB rms 95 SFDR DCS ON 90 8 SNR/SFDR (dBc) NUMBER OF HITS (1M) 10 6 4 85 80 SFDR DCS OFF 75 SNR DCS ON 70 2 65 N–2 N–1 N N+1 N+2 N+3 OUTPUT CODE 06909-140 N–3 60 20 40 60 80 DUTY CYCLE (%) Figure 40. AD9600 Grounded Input Histogram 06909-143 SNR DCS OFF 0 Figure 43. AD9600-150 SNR/SFDR vs. Duty Cycle with fIN1 = 10.3 MHz 95 0.10 90 SNR/SFDR (dBc) INL ERROR (LSB) SFDR 85 0.05 0 80 75 70 65 –0.
PAGE 23
AD9600 THEORY OF OPERATION The AD9600 dual ADC design can be used for diversity reception of signals, where the ADCs are operating identically on the same carrier but from two separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample any fS/2 frequency segment from dc to 200 MHz using appropriate low-pass or band-pass filtering at the ADC inputs with little loss in ADC performance.
PAGE 24
AD9600 An alternative to using a transformer-coupled input at frequencies in the second Nyquist zone is to use the AD8352 differential driver. An example is shown in Figure 50. See the AD8352 data sheet for more information. ADC. The output common-mode voltage of the AD8138 is easily set with the CML pin of the AD9600 (see Figure 46), and the driver can be configured in a Sallen-Key filter topology to band limit the input signal. AVDD VIN+ R 499Ω AD9600 C AD8138 R 523Ω VIN– CML 499Ω Table 10.
PAGE 25
AD9600 VOLTAGE REFERENCE VIN + A/VIN + B VIN – A/VIN – B A stable and accurate voltage reference is built into the AD9600. The input range can be adjusted by varying the reference voltage applied to the AD9600, using either the internal reference or an externally applied reference voltage. The input span of the ADC tracks reference voltage changes linearly. The various reference modes are summarized in this section.
PAGE 26
AD9600 External Reference Operation The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve the thermal drift characteristics. Figure 54 shows the typical drift characteristics of the internal reference in 1.0 V mode. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9600 while preserving the fast rise and fall times of the signal that are critical to low jitter performance. 2.0 1.5 1.
PAGE 27
AD9600 In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be driven directly from a CMOS gate, and the CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 60). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages of up to 3.6 V and therefore offers several selections for the drive logic voltage.
PAGE 28
AD9600 This maximum current occurs when every output bit switches on every clock cycle, that is, a full-scale square wave at the Nyquist frequency, fCLK/2. In practice, the DRVDD current is established by the average number of output bits switching, which is determined by the sample rate and the characteristics of the analog input signal. Reducing the capacitive load presented to the output drivers can minimize digital power consumption.
PAGE 29
AD9600 Table 12. SCLK/DFS Mode Selection (External Pin Mode) TIMING Voltage at Pin AGND AVDD The AD9600 provides latched data with a pipeline delay of 12 clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal. SCLK/DFS Offset binary (default) Twos complement SDIO/DCS DCS disabled DCS enabled (default) Digital Output Enable Function (OEB) The AD9600 has a flexible three-state ability for the digital output pins.
PAGE 30
AD9600 ADC OVERRANGE AND GAIN CONTROL In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overflow indicator provides after-the-fact information on the state of the analog input that is of limited usefulness. Therefore, it is helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs.
PAGE 31
AD9600 When the fast detect mode select bits are set to 0b001, 0b010, or 0b011, a subset of the fast detect output pins is available. In these modes, the fast detect output pins have a latency of six clock cycles. Table 16 shows the corresponding ADC input levels when the fast detect mode select bits are set to 0b001 (that is, when ADC fast magnitude is presented on the FD [3:1] pins). Table 16.
PAGE 32
AD9600 Increment Gain (IG) and Decrement Gain (DG) fine lower threshold register is a 13-bit register that is compared with the magnitude at the output of the ADC. This comparison is subject to the ADC clock latency but allows a finer, more accurate comparison. The fine threshold magnitude is defined in Equation 1 (see the Fine Upper Threshold (F_UT) section). The increment gain and decrement gain indicators are intended to be used together to provide information to enable external gain control.
PAGE 33
AD9600 SIGNAL MONITOR The signal monitor result values can be obtained from the part by reading back Register 0x116 to Register 0x11B, using the SPI port or the signal monitor SPORT output. The output contents of the SPI-accessible signal monitor registers are set via the two signal monitor mode bits of the signal monitor control register (Address 0x112). Both ADC channels must be configured for the same signal monitor mode.
PAGE 34
AD9600 the value of the accumulator is reset to the first input sample signal power, and the accumulation continues with the subsequent input samples. cycle. If the input signal has a magnitude greater than the value set in the fine upper threshold register, the value in the internal count register (not accessible to the user) is incremented by 1. Figure 68 illustrates the rms magnitude monitoring logic. The initial value of the internal count register is set to 0.
PAGE 35
AD9600 DC CORRECTION DC Correction Enable Bits Because the dc offset of the ADC may be significantly larger than the signal being measured, a dc correction circuit is included to null the dc offset before measuring the power. The dc correction circuit can also be switched into the main signal path, but this may not be appropriate if the ADC is digitizing a time-varying signal with significant dc content, such as GSM.
PAGE 36
AD9600 BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST The AD9600 includes built-in test features to enable verification of the integrity of each channel as well as to facilitate board level debugging. A BIST feature is included that verifies the integrity of the digital datapath of the AD9600. Various output test options are also provided to place predictable values on the outputs of the AD9600. BUILT-IN SELF-TEST (BIST) The BIST is a thorough test of the digital portion of the selected AD9600 signal path.
PAGE 37
AD9600 CHANNEL/CHIP SYNCHRONIZATION The AD9600 has a SYNC input that offers the user flexible synchronization options for synchronizing the internal blocks. The clock divider sync feature is useful to guarantee synchronized sample clocks across multiple ADCs. The signal monitor block can also be synchronized using the SYNC input, allowing properties of the input signal to be measured during a specific period.
PAGE 38
AD9600 SERIAL PORT INTERFACE (SPI) The AD9600 SPI allows the user to configure the converter for specific functions or operations through a structured register space provided inside the ADC. This may provide the user with additional flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, which are documented in the Memory Map section.
PAGE 39
AD9600 CONFIGURATION WITHOUT THE SPI SPI ACCESSIBLE FEATURES In applications that do not interface to the SPI control registers, the SDIO/DCS pin, the SCLK/DFS pin, the SMI SDO/OEB pin, and the SMI SCLK/PDWN pin serve as standalone CMOScompatible control pins. When the device is powered up, it is assumed that the user intends to use the pins as static control lines for the duty cycle stabilizer, output data format, output enable, and power-down feature control.
PAGE 40
AD9600 MEMORY MAP READING THE MEMORY MAP TABLE Logic Levels Each row in the memory map registers table (Table 22) has eight bit locations. The memory map is divided into four sections: the chip configuration registers (Address 0x00 to Address 0x02), the channel index and transfer registers (Address 0x05 and Address 0xFF), the ADC functions registers (Address 0x08 to Address 0x25), and the digital feature control registers (Address 0x100 to Address 0x11B).
PAGE 41
AD9600 MEMORY MAP All address and bit locations that are not included in Table 22 are currently not supported for this device. Table 22.
PAGE 42
AD9600 Addr (Hex) 0x0E 0x10 0x14 Register Name BIST Enable (Local) Offset Adjust (Local) Output Mode Bit 7 (MSB) Open Bit 6 Open Open Open Drive strength 0 V to 3.3 V CMOS or ANSI LVDS: 1 V to 1.
PAGE 43
AD9600 Addr (Hex) 0x10A 0x10B 0x10C 0x10D 0x10E 0x10F 0x110 0x111 Register Name Increase Gain Dwell Time Register 0 (Local) Increase Gain Dwell Time Register 1 (Local) Signal Monitor DC Correction Control (Global) Signal Monitor DC Value Channel A Register 0 (Global) Signal Monitor DC Value Channel A Register 1 (Global) Signal Monitor DC Value Channel B Register 0 (Global) Signal Monitor DC Value Channel B Register 1 (Global) Signal Monitor SPORT Control (Global) 0x112 Signal Monitor Control (Glob
PAGE 44
AD9600 Addr (Hex) 0x118 0x119 0x11A 0x11B Register Name Signal Monitor Result Channel A Register 2 (Global) Signal Monitor Result Channel B Register 0 (Global) Signal Monitor Result Channel B Register 1 (Global) Signal Monitor Result Channel B Register 2 (Global) Bit 7 (MSB) Open Open Bit 6 Open Open Bit 5 Open Open Bit 4 Open Bit 0 Bit 3 Bit 2 Bit 1 (LSB) Signal Monitor Value Channel A [19:16] Default Value (Hex) Default Notes/ Comments Read only.
PAGE 45
AD9600 Increase Gain Dwell Time (Register 0x10A and Register 0x10B) Register 0x10A, Bits [7:0]—Increase Gain Dwell Time [7:0] Register 0x10B, Bits [7:0]—Increase Gain Dwell Time [15:8] These registers are programmed with the dwell time in ADC clock cycles. The signal must be below the fine lower threshold value before the increase gain (IG) indicator is asserted.
PAGE 46
AD9600 Signal Monitor Period (Register 0x113 to Register 0x115) Register 0x113, Bits [7:0]—Signal Monitor Period [7:0] Register 0x114, Bits [7:0]—Signal Monitor Period [15:8] Register 0x115, Bits [7:0]—Signal Monitor Period [23:16] This 24-bit value sets the number of clock cycles over which the signal monitor performs its operation. Although this register defaults to 64 (0x40), the minimum value for this register is 128 (0x80) cycles—writing values less than 128 can cause inaccurate results.
PAGE 47
AD9600 APPLICATIONS INFORMATION DESIGN GUIDELINES When designing the AD9600 into a system, the designer should, before starting design and layout, become familiar with these guidelines, which discuss the special circuit connections and layout requirements for certain pins. Power and Ground Recommendations When connecting power to the AD9600, the designer should use two separate 1.8 V supplies: one supply should be used for AVDD and DVDD and a separate supply for DRVDD.
PAGE 48
AD9600 EVALUATION BOARD The AD9600 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially using the double-balun configuration (default) or an AD8352 differential driver. The ADC can also be driven in a single-ended fashion. Separate power pins are provided to isolate the DUT from the AD8352 drive circuitry.
PAGE 49
AD9600 DEFAULT OPERATION AND JUMPER SELECTION SETTINGS The following is a list of the default and optional settings, or modes, allowed on the AD9600 evaluation board. POWER Connect the switching power supply that is provided with the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P500. VIN The evaluation board is set up for a double-balun configuration analog input with an optimum 50 Ω impedance matching from 70 MHz to 200 MHz.
PAGE 50
AD9600 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION 1. Remove C1, C17, C18, and C117 in the default analog input path. This section provides a brief description of the alternative analog input drive configuration using the AD8352. When using this drive option, some additional components need to be populated. For more details on the AD8352 differential driver, including how it works and its optional pin settings, consult the AD8352 data sheet. 2. Populate C8 and C9 with 0.
PAGE 51
AIN+ AIN- S1 2 S2 1 2 1 INA+ R1 57.6OHM R28 R121 0 OHM RES0402 R120 0 OHM 0.1U C9 0.1U C117 0.1U C1 0 OHM R2 INA+ 0.1U C47 INA- 4 5 T10 R54 3 0.1U C11 0.1U C10 4.12 K DNP C125 .3PF 5 4 5 4 ETC1-1-1 3 P T1 1ADT1_1W T6 2 3 T7 0 OHM R110 S 1 2 3 CML 1 2 3 ETC1-1-1 3 S T2 P 5 4 0.1U C18 0.1U C17 DEFAULT AMPLIFIER INPUT PATH 0 OHM P 1 S 2 ETC1-1-13 0 OHM F 0.1U R29 R35 R31 24.9OHM 24.
PAGE 52
AIN+ AIN- S4 S3 1 1 57.6OHM R52 57.6OHM R51 RES0402 0 OHM R123 RES0402 0 OHM R122 INB- 0.1U C31 INB+ 0.1U C6 0.1U C28 0 OHM R67 INB- 4 5 R66 S F 3 2 1 DNP 0.1U 0.1U C39 .3PF C128 0.1U 4 5 T8 P T3 4 5 6 S ETC1-1-13 3 2 1 ADT1_1W T 0 OHM R111 3 2 1 CML 4 5 P T4 S ETC1-1-13 3 2 1 R132 DNP R133 0 OHM R6 0 OHM DEFAULT AMPLIFIER INPUT PATH 0 OHM R55 T11 C51 P ETC1-1-1 3 0 OHM R134 R135 0.1U R128 INB+ 24.9OHM 24.
PAGE 53
S6 SMA200U P ENC\ ENC S5 1 1 R30 R7 R8 57.6OHM 57.6OHM 0 OHM 10KOHM 10KOHM R85 R82 0 OHM R3 0 OHM R90 Figure 76. Evaluation Board Schematic, DUT Clock Input 0.001U C77 0.001U C94 0.001U C63 0.001U 4 5 0.1U OPT_CLK- 3 S 2 T5 ETC1-1-13 P 1 6 T9 5 4 ADT1_1W T 1 2 3 C56 OPT_CLK+ 0.1U 0.001U C79 0 OHM R33 0 OHM R32 0.001U C78 OPT_CLK- ALTCLK- OPT_CLK+ ALTCLK+ R78 0 OHM R79 0 OHM R101 0 OHM R99 0 OHM R83 0.1U C21 24.9OHM R84 0.1U C20 24.
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1 S7 1 AD9516 CLK IN TEST C104 0.1U VS_OUT_D R VCXO_CLK- RES0402 0 OHM R125 RES0402 R89 C100 0.1U 0 OHM R124 VCXO_CLK+ LD 0 OHM R10 49.9OHM C101 0.1U C98 0.1U 0.1U C143 0.1U C142 C80 18PF C99 0.1U VS SCLK VCP BYPASS_LDO 9 LF BYPASS_LDO CLK C96 0.1U SCLK 16 NC1 15 CLKB 14 13 C97 0.
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CP Figure 78. Evaluation Board Schematic, Optional AD9516 Loop Filter/VCO and SYNC Input Rev. B | Page 55 of 72 BYPASS_LDO VAL R136 SYNC S12 SMA200U P 2 R98 VAL C90 SEL RES060 3 57.6OHM R45 C89 SEL R93 VAL VAL R137 C25 SEL C91 C144 SEL 0.1U Charge Pump Filter 1 VAL R97 3 2 A2 NL27WZ04 C92 SEL GND U3 4 5 6 RES0402 0 OHM R117 RES0402 0 OHM R116 Y2 VCC Y1 R46 LF RES0402 TP1 1 R104 R87 OSCVECTRON_VS50 0 RES0402 0 OHM U25 4 OUT2 3 GND 6 VCC 5 OUT1 24.
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Rev. B | Page 56 of 72 1 Figure 79. Evaluation Board Schematic, DUT NC D5A NC DVDD FD3B FD2B FD1B D9A(MSB) FD0B FD0A SYNC FD1A SPI_CSB FD2A CLK- FD3A CLK+ 57 52 51 50 49 C137 0.001U D4A C121 0.1U C120 0.1U NC U1 SPI_SCLK/DFS SPI_SDIO/DCS DRVDD C109 0.1U C40 0.1U 48 47 AVDD3 AVDD2 VIN+B VIN-B RBIAS CML NC C122 0.001U C126 0.001U SPI_SCLK SPI_SDIO 46 45 44 43 42 41 0.001U DRGND C127 0.001U R64 AVDD AVDD VIN+B VIN-B CML C36 0.
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D3A D2A Figure 80.
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Rev. B | Page 58 of 72 CSB SDO SDI SCLK CSB_2 V_DIG CSB SCLK 10KOHM RES0402 C13 0.1U R24 A2 GND A1 3 2 1 RES0402 A2 Y1 Y2 VCC Y1 U8 NC7WZ07P6 X Y2 VCC NC7WZ16P6 X GND A1 R19 1KOHM RES0603 10KOHM 3 2 1 RES0402 R18 U7 4 5 6 4 5 6 SDO V_DIG C81 0.
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POWER_JAC K 2 Figure 82. Evaluation Board Schematic, Power Supply Rev. B | Page 59 of 72 P4 P3 P2 P1 VCP VS DRVDDIN SJ35 P4 6 P6 5 P5 4 P4 3 P3 2 P2 1 1 AVDDIN SMDC110F C41 10U F2 OPTIONALPOWERSUPPLYINPUTS P3 1 P1 1 3 L6 IND1210 10UH 10uh L10 IND1210 L9 IND1210 10UH 1 2 1 2 2 CR7 2 C53 10U C102 10U C52 10U BNX-016 3 PSG 1 BIAS C58 0.1U C103 0.1U C57 0.
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PWR_IN PWR_IN Rev. B | Page 60 of 72 Figure 83. Evaluation Board Schematic, Power Supply (Continued) PAD ADP333 9 VCP 5 C119 10U GND OUT 1 OUT2 2 FB 3 VR2 OUT OUT C124 10U VS_OUT_D R Power Supply ByPass Capacitors VCP SD 6 8 IN 7 IN2 ADP3334 C132 1U IN VR6 C135 1U 3 C133 1U PAD ADP333 9 4 GND 1 4 GND 1 IN VS C136 1U C134 1U C118 10U R25 VR5 140KOHM R15 0.001U C95 SJ36 78.
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AD9600 06909-185 EVALUATION BOARD LAYOUTS Figure 84. Evaluation Board Layout, Primary Side Rev.
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06909-186 AD9600 Figure 85. Evaluation Board Layout, Ground Plane Rev.
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06909-187 AD9600 Figure 86. Evaluation Board Layout, Power Plane Rev.
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06909-188 AD9600 Figure 87. Evaluation Board Layout, Power Plane Rev.
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06909-189 AD9600 Figure 88. Evaluation Board Layout, Ground Plane Rev.
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06909-190 AD9600 Figure 89. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev.
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06909-191 AD9600 Figure 90. Evaluation Board Layout, Silkscreen, Primary Side Rev.
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06909-192 AD9600 Figure 91. Evaluation Board Layout, Silk Screen, Secondary Side Rev.
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AD9600 BILL OF MATERIALS Table 23. Evaluation Board Bill of Materials (BOM) 1, 2 Item 1 2 Qty 1 55 3 1 Reference Designator AD9600CE_REVB C1 to C3, C6, C7, C13, C14, C17, C18, C20 to C26, C32, C57 to C61, C65 to C76, C81 to C83, C96 to C101, C103, C105, C107, C108, C110 to C116, C145 C80 4 2 C5, C84 5 10 6 13 7 10 8 1 C33, C35, C63, C93 to C95, C122, C126, C127, C137 C15, C42 to C45, C129 to C136 C27, C41, C52 to C54, C62, C102, C118, C119, C124 CR5 9 2 CR6, CR9 Description PCB 0.
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AD9600 Item 26 Qty 1 Reference Designator R16 27 3 R17, R22, R23 28 7 29 3 R18, R24, R63, R65, R82, R118, R140 R19, R20, R21 30 9 31 5 R26, R27, R43, R46, R47, R70, R71, R73, R74 R57, R59 to R62 32 1 R58 33 1 R76 34 4 S2, S3, S5 ,S12 Description 261 Ω, 0603, 1/10 W, 1% resistor 100 kΩ, 0603, 1/10 W, 1% resistor 10 kΩ, 0402, 1/16 W, 1% resistor 1 kΩ, 0603, 1/10 W, 1% resistor 33 Ω, 0402, 1/16 W, 5% resistor Package R0603 Manufacturer NIC Components Mfg.
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AD9600 OUTLINE DIMENSIONS 0.60 MAX 9.00 BSC SQ 0.60 MAX 64 1 49 48 PIN 1 INDICATOR PIN 1 INDICATOR 8.75 BSC SQ 0.50 BSC 0.50 0.40 0.30 1.00 0.85 0.80 16 17 33 32 0.25 MIN 7.50 REF 0.80 MAX 0.65 TYP 12° MAX FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 7.25 7.10 SQ 6.95 EXPOSED PAD (BOTTOM VIEW) 0.
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AD9600 ORDERING GUIDE Model AD9600ABCPZ-150 1,2 AD9600ABCPZ-1251,2 AD9600ABCPZ-1051,2 AD9600BCPZ-1501 AD9600BCPZ-1251 AD9600BCPZ-1051 AD9600-150EBZ1 1 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 64-Lead Lead Frame Chip Scale Pac