Datasheet

AD9572
Rev. B | Page 8 of 20
TIMING DIAGRAMS
SINGLE-ENDED
CMOS
5pF LOAD
80%
20%
t
RC
t
FC
0
7498-006
DIFFERENTIAL
LVPECL
80%
0%
20%
t
RP
V
OD
t
FP
0
7498-022
Figure 5. CMOS Timing, Single-Ended, 5 pF Load
Figure 3. LVPECL Timing, Differential
DIFFERENTIAL
LVDS
80%
0%
20%
t
RL
V
OD
t
FL
0
7498-023
Figure 4. LVDS Timing, Differential