Datasheet

AD9572
Rev. B | Page 4 of 20
Parameter Min Typ Max Unit Test Conditions/Comments
PLL Noise (125 MHz LVPECL Output)
At 1 kHz −122 dBc/Hz 33.33 MHz output disabled
At 10 kHz −127 dBc/Hz 33.33 MHz output disabled
At 100 kHz −128 dBc/Hz 33.33 MHz output disabled
At 1 MHz −148 dBc/Hz 33.33 MHz output disabled
At 10 MHz −152 dBc/Hz 33.33 MHz output disabled
At 30 MHz −153 dBc/Hz 33.33 MHz output disabled
PLL Noise (100 MHz LVPECL Output)
At 1 kHz −122 dBc/Hz 33.33 MHz output disabled
At 10 kHz −128 dBc/Hz 33.33 MHz output disabled
At 100 kHz −130 dBc/Hz 33.33 MHz output disabled
At 1 MHz −148 dBc/Hz 33.33 MHz output disabled
At 10 MHz −150 dBc/Hz 33.33 MHz output disabled
At 30 MHz −151 dBc/Hz 33.33 MHz output disabled
PLL Noise (33.33 MHz CMOS Output)
At 1 kHz −130 dBc/Hz
At 10 kHz −138 dBc/Hz
At 100 kHz −139 dBc/Hz
At 1 MHz −152 dBc/Hz
At 5 MHz −152 dBc/Hz
Phase Noise (25 MHz CMOS Output)
At 1 kHz −133 dBc/Hz
At 10 kHz −142 dBc/Hz
At 100 kHz −148 dBc/Hz
At 1 MHz −148 dBc/Hz
At 5 MHz −148 dBc/Hz
Spurious Content
1
−70 dBc Dominant amplitude, all outputs active
PLL Figure of Merit −217.5 dBc/Hz
1
When the 33.33 MHz, 100 MHz, and 125 MHz clocks are enabled simultaneously, a worst-case −50 dBc spurious content might be presented on Pin 21 and Pin 22 only.
LVDS CLOCK OUTPUT JITTER
Typical (typ) is given for V
S
= 3.3 V, T
A
= 25°C, unless otherwise noted.
Table 2.
Jitter Integration
Bandwidth (Typ) 100 MHz 106.25 MHz
125 MHz 33M
= Off/On
1
156.25 MHz Unit Test Conditions/Comments
12 kHz to 20 MHz 0.51 0.44 0.42/0.88 0.42
ps
rms
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 2 × 106.25 MHz
1.875 MHz to
20 MHz
0.19
ps
rms
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 2 × 106.25 MHz
637 kHz to 10 MHz 0.22
ps
rms
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 2 × 106.25 MHz
200 kHz to 10 MHz 0.32 0.25/0.78
ps
rms
LVDS output frequency combinations
are 1 × 156.25 MHz, 1 × 100 MHz, 1 ×
125 MHz, 2 × 106.25 MHz
12 kHz to 35 MHz 0.50 (off only)
ps
rms
LVDS output frequency combinations
are 1 × 156.25 MHz, 2 × 125 MHz, 2 ×
106.25 MHz
1
The typical 125 MHz rms jitter data is collected from the differential pair, Pin 21 and Pin 22, unless otherwise noted.