Datasheet

AD9572
Rev. B | Page 16 of 20
THEORY OF OPERATION
XTAL
OSC
REFCLK
REFSEL
V
S
VS
GNDBYPASS1
1
0
AD9572
DIVIDE
BY 5
DIVIDE
BY 4
DIVIDE
BY 5
DIVIDE
BY 3
33M
FORCE_LOW
CMOS
33.33MHz
0
1
1
0
125MHz/100MHz
LVPECL/
LVDS
100M/125M
100M/125M
100M/125M
100M/125M
125MHz/100MHz
LVPECL/
LVDS
25M
CMOS
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
DIVIDE
BY 17
DIVIDE
BY 5
DIVIDE
BY 4
V
LDO
VCO
106M
106M
LVPECL/
LVDS
106.25MHz
106M
106M
LDO
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
DIVIDE
BY 25
DIVIDE
BY 4
DIVIDE
BY 4
V
LDO
VCO
LDO
156M
156M
156.25MHz
LVPECL/
LVDS
BYPASS2
07498-013
LEVEL
DECODE
FREQSEL
Figure 17. Detailed Block Diagram
Figure 17 shows a block diagram of the AD9572. The chip
combines dual PLL cores, which are configured to generate the
specific clock frequencies required for networking applications
without any user programming. This PLL is based on proven
Analog Devices synthesizer technology, noted for its exceptional
phase noise performance. The AD9572 is highly integrated and
includes loop filters, regulators for supply noise immunity, all
the necessary dividers with multiple output buffers in a choice
of formats, and a crystal oscillator. A user need only supply a
25 MHz reference clock or an external crystal to implement an
entire line card clocking solution that does not require any
processor intervention. A copy of the 25 MHz reference source
is also available.
OUTPUTS
Tabl e 14 provides a summary of the outputs available.
Table 14. Output Formats
Frequency Format Copies
25 MHz CMOS 1
106.25 MHz LVPECL/LVDS 2
156.25 MHz LVPECL/LVDS
1
100 MHz or 125 MHz LVPECL/LVDS
2
33.33 MHz CMOS 1
Note that the pins labeled 100M/125M can provide 100 MHz or
125 MHz by strapping the FREQSEL pin as shown in Tabl e 15.