Datasheet

AD9572
Rev. B | Page 12 of 20
50
50
50
50
50
50
50
50
50
07498-025
C
D
V
S
C
D
V
S
0.22µF
V
S
V
S
V
S
C
D
50
50
C
D
V
S
C
D
V
S
25MHz
C
X
= 22pF
C
X
= 22pF
50
T
O CMOS
INPUT
C
D
= 100nF||10nF
C
D
C
D
V
S
V
S
C
D
V
S
C
D
V
S
C
D
0.22µF
V
S
C
D
V
S
C
D
V
S
C
D
V
S
TO CMOS
INPUT
AD9572
106M
100M/125M
VS
VS
VS
VS
33M
FREQSEL
106M
106M
VS
VS
VS
VS
GND
GND
NC
VS
25M
VS
XO
XO
REFCLK
REFSEL
GND
BYPASS1
TEST
FORCE_LOW
VS
TEST
TEST
VS
VS
156M
100M/125M
BYPASS2
106M
100M/125M
100M/125M
156M
VS VS
127 127
83 83
V
S
V
S
127 127
83 83
VS VS
127 127
127
127
83
83
83
83
VS VS
127 127
83 83
Figure 8. Typical Application Schematic, LPECL Format Outputs, 1 × 25 MHz, 1 × 156.25 MHz, 2 × 125 MHz, and 2 × 106.25 MHz