Datasheet
AD9572
Rev. B | Page 11 of 20
Pin No. Mnemonic Description
33 VS Power Supply Connection for the 106.25 MHz LVDS Output Buffer and Output Dividers.
35 VS Power Supply Connection for the FC VCO.
37 FORCE_LOW
Forces the 33.33 MHz output into a low state.
38 N/A
Short to Pin 36.
39 VS
Power Supply Connection for the FC PLL.
40 VS Power Supply Connection for Miscellaneous Logic.
1
The exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to
ground (GND).
07498-024
50Ω
50Ω
C
D
V
S
C
D
V
S
C
D
V
S
C
D
V
S
R
T
= 100Ω
0.22µF
C
D
= 100nF||10nF
C
D
V
S
C
D
V
S
V
S
C
D
R
T
= 100Ω
50Ω
50Ω
R
T
= 100Ω
50Ω
50Ω
C
D
V
S
C
D
V
S
25MHz
C
X
= 22pF
C
X
= 22pF
50Ω
T
O CMOS
INPUT
C
D
V
S
C
D
V
S
C
D
V
S
C
D
V
S
R
T
= 100Ω
50Ω
50Ω
R
T
= 100Ω
50Ω
50Ω
50Ω
TO CMOS
INPUT
AD9572
106M
100M/125M
VS
VS
VS
VS
33M
FREQSEL
106M
106M
VS
VS
VS
VS
GND
GND
NC
VS
25M
VS
XO
XO
REFCLK
REFSEL
GND
BYPASS1
TEST
FORCE_LOW
VS
TEST
TEST
VS
VS
156M
100M/125M
BYPASS2
106M
100M/125M
100M/125M
156M
0.22µF
Figure 7. Typical Application Schematic, LVDS Format Outputs, 1 × 25 MHz, 1 × 156.25 MHz, 2 × 125 MHz, and 2 × 106.25 MHz