Datasheet

Data Sheet AD9559
Rev. C | Page 99 of 120
DPLL_1 SETTINGS FOR REFERENCE INPUT B (REFB) (REGISTER 0x0567 TO REGISTER 0x0573)
Table 138. DPLL_1 REFB Priority Setting
Address Bits Bit Name Description
0x0567
[7:3]
Reserved
Default: 00000b.
[2:1] REFB priority These bits set the priority level (0 to 3) of REFA relative to the other input references.
00 (default) = 0 (highest).
01 = 1.
10 = 2.
11 = 3.
0 Enable REFB This bit enables DPLL_1 to lock to REFB.
0 (default) = REFB is not enabled for use by DPLL_1.
1 = REFB is enabled for use by DPLL_1.
Table 139. DPLL_1 REFB Loop BW Scaling Factor
Address Bits Bit Name Description
0x0568 [7:0] DPLL loop BW scaling factor
(unit of 0.1 Hz)
Digital PLL loop bandwidth scaling factor, Bits[7:0] (default: 0xF4).
0x0569 [7:0] Digital PLL loop bandwidth scaling factor, Bits[15:8] (default: 0x01).
Default for Register 0x0568 to Register 0x056A: 0x01F4 = 500 (50 Hz loop BW.
The loop bandwidth should always be less than the DPLL phase detector frequency
divided by 20. The DPLL may not lock reliably if the DPLL loop BW is <50 Hz and a crystal
oscillator is used for the system clock. See the Choosing the SYSCLK Source section for
more information.
0x056A [7:2] Reserved Default: 0x00.
1 Base loop filter selection 0 = base loop filter with normal (70°) phase margin (default).
1 = base loop filter with high phase margin.
(≤0.1 dB peaking in the closed-loop transfer function for loop BWs ≤ 2 kHz. Setting this
bit is also recommended for loop BW > 2kHz.)
0 Reserved Default: 0b.
Table 140. DPLL_1 REFB Integer Part of Feedback Divider
Address
Bits
Bit Name
Description
0x056B [7:0] Integer Part N1 DPLL integer feedback divider (minus 1), Bits[7:0] (default: 0xCB)
0x056C [7:0] DPLL integer feedback divider, Bits[15:8] (default: 0x07)
0x056D [7:1] Reserved Default: 0x00
0 Integer Part N1 DPLL integer feedback divider, Bit 16 (default: 0b)
Default for Register 0x056B to Register 0x056D: 0x007CB (which equals N1 = 1996)
Table 141. DPLL_1 REFB Fractional Part of Fractional Feedback Divider FRAC1
Address Bits Bit Name Description
0x056E [7:0] Digital PLL fractional
feedback divider—FRAC1
The numerator of the fractional-N feedback divider, Bits[7:0] (default: 0x04)
0x056F [7:0] The numerator of the fractional-N feedback divider, Bits[15:8] (default: 0x00)
0x0570 [6:0] The numerator of the fractional-N feedback divider, Bits[22:16] (default: 0x00)
7 Reserved Default: 0b.
Table 142. DPLL_1 REFB Modulus of Fractional Feedback Divider MOD1
Address Bits Bit Name Description
0x0571 [7:0] Digital PLL feedback divider
modulus—MOD1
The denominator of the fractional-N feedback divider, Bits[7:0] (default: 0x05)
0x0572 [7:0] The denominator of the fractional-N feedback divider, Bits[15:8] (default: 0x00)
0x0573
[6:0] The denominator of the fractional-N feedback divider, Bits[22:16] (default: 0x00)
7
Reserved
Default: 0b.