Datasheet
Data Sheet AD9559
Rev. C | Page 97 of 120
Table 127. DPLL_1 REFC Modulus of Fractional Feedback Divider Mod1
Address Bits Bit Name Description
0x054A [7:0] Digital PLL feedback
divider modulus—MOD1
The denominator of the fractional-N feedback divider, Bits[7:0] (default: 0x05)
0x054B [7:0] The denominator of the fractional-N feedback divider, Bits[15:8] (default: 0x00)
0x054C [6:0] The denominator of the fractional-N feedback divider, Bits[22:16] (default: 0x00)
7
Reserved
Default: 0b
DPLL_1 SETTINGS FOR REFERENCE INPUT D (REFD) (REGISTER 0x054D TO REGISTER 0x0559)
Table 128. DPLL_1 REFD Priority Setting
Address Bits Bit Name Description
0x054D [7:3] Reserved Default: 00000b.
[2:1] REFD priority These bits set the priority level (0 to 3) of REFD relative to the other input references.
00 (default) = 0 (highest).
01 = 1
10 = 2
11 = 3
0 Enable REFD This bit enables DPLL_1 to lock to REFD.
0 = REFD is not enabled for use by DPLL_1
1 (default) = REFD is enabled for use by DPLL_1
Table 129. DPLL_1 REFD Loop BW Scaling Factor
Address Bits Bit Name Description
0x054E [7:0] DPLL loop BW scaling factor
(unit of 0.1 Hz)
Digital PLL loop bandwidth scaling factor, Bits[7:0] (default: 0xF4).
0x054F [7:0] Digital PLL loop bandwidth scaling factor, Bits[15:8] (default: 0x01).
The default for Register 0x054E and Register 0x054F = 0x01F4 = 500 (50 Hz loop BW).
The loop bandwidth should always be less than the DPLL phase detector frequency
divided by 20. The DPLL may not lock reliably if the DPLL loop BW is <50 Hz and a crystal
is used for the system clock. See the Choosing the SYSCLK Source section for details.
0x0550
[7:2]
Reserved
Default: 0x00.
1 Base loop filter selection 0 = base loop filter with normal (70°) phase margin (default).
1 = base loop filter with high phase margin.
(≤0.1 dB peaking in the closed-loop transfer function for loop BW ≤ 2 kHz. Setting this
bit is also recommended for loop BW > 2 kHz.)
0 Reserved Default: 0b.
Table 130. DPLL_1 REFD Integer Part of Feedback Divider
Address
Bits
Bit Name
Description
0x0551 [7:0] Integer Part N1 DPLL integer feedback divider (minus 1), Bits[7:0] (default: 0xCB).
0x0552 [7:0] DPLL integer feedback divider, Bits[15:8] (default: 0x07).
0x0553 [7:1] Reserved Default: 0x00.
0 Integer Part N1 DPLL integer feedback divider, Bit 16 (default: 0b).
The default for Register 0x0551 to Register 0x0553: 0x007CB (which equals N1 = 1996).
Table 131. DPLL_1 REFD Fractional Part of Fractional Feedback Divider FRAC1
Address Bits Bit Name Description
0x0554 [7:0] Digital PLL fractional
feedback divider—FRAC1
The numerator of the fractional-N feedback divider, Bits[7:0] (default: 0x04)
0x0555 [7:0] The numerator of the fractional-N feedback divider, Bits[15:8] (default: 0x00)
0x0556 [6:0] The numerator of the fractional-N feedback divider, Bits[22:16] (default: 0x00)
7
Reserved
Default: 0b
Table 132. DPLL_1 REFD Modulus of Fractional Feedback Divider MOD1
Address Bits Bit Name Description
0x0557 [7:0] Digital PLL feedback divider
modulus—MOD1
The denominator of the fractional-N feedback divider, Bits[7:0] (default: 0x05)
0x0558 [7:0] The denominator of the fractional-N feedback divider, Bits[15:8] (default: 0x00)
0x0559 [6:0] The denominator of the fractional-N feedback divider, Bits[22:16] (default: 0x00)
7
Reserved
Default: 0b