Datasheet
AD9559 Data Sheet
Rev. C | Page 96 of 120
Table 122. OUT1B Divider Setting
Address Bits Bit Name Description
0x052C [7:0] Q1_B divider 10-bit channel divider, Bits[7:0] (LSB).
Division equals channel divider, Bits[9:0] + 1.
([9:0] = 0 is divide-by-1, [9:0] = 1 is divide-by-2…[9:0] = 1023 is divide-by-1024).
0x052D [7:2] Reserved Default: 000000b.
[1:0] Q1_B divider 10-bit channel divider, Bits[9:8] (MSB), Bits[1:0].
0x052E [7:6] Reserved Default: 00b.
[5:0] Q1_B divider phase Divider initial phase after sync relative to the divider input clock (from the P1 divider output).
LSB is ½ of a period of the divider input clock.
Phase = 0 is no phase offset.
Phase = 1 is ½ a period offset.
DPLL_1 SETTINGS FOR REFERENCE INPUT C (REFC) (REGISTER 0x0540 TO REGISTER 0x054C)
Table 123. DPLL_1 REFC Priority Setting
Address Bits Bit Name Description
0x0540 [7:3] Reserved Reserved.
[2:1] REFC priority These bits set the priority level (0 to 3) of REFD relative to the other input references.
00 (default) = 0 (highest).
01 = 1.
10 = 2.
11 = 3.
0 Enable REFC This bit enables DPLL_1 to lock to REFC.
0 = REFC is not enabled for use by DPLL_1.
1 (default) = REFC is enabled for use by DPLL_1.
Table 124. DPLL_1 REFC Loop BW Scaling Factor
Address Bits Bit Name Description
0x0541 [7:0] DPLL loop BW scaling factor
(unit of 0.1 Hz)
Digital PLL loop bandwidth scaling factor, Bits[7:0] (default: 0xF4).
0x0542 [7:0] Digital PLL loop bandwidth scaling factor, Bits[15:8] (default: 0x01).
Default for Register 0x0541 and Register 0x0542: 0x01F4 = 500 (50 Hz loop BW).
The loop bandwidth should always be less than the DPLL phase detector frequency divided
by 20. The DPLL may not lock reliably if the DPLL loop BW is <50 Hz and a crystal is used
for the system clock. See the Choosing the SYSCLK Source section for details.
0x0543 [7:2] Reserved Default: 0x00.
1 Base loop filter selection 0 = base loop filter with normal (70°) phase margin (default).
1 = base loop filter with high phase margin.
(≤0.1 dB peaking in the closed-loop transfer function for loop BW ≤ 2 kHz. Setting this bit
is also recommended for loop BW > 2 kHz.)
0 Reserved Default: 0b.
Table 125. DPLL_1 REFC Integer Part of Feedback Divider
Address Bits Bit Name Description
0x0544 [7:0] Integer Part N1 DPLL integer feedback divider (minus 1), Bits[7:0] (default: 0xCB).
0x0545 [7:0] DPLL integer feedback divider, Bits[15:8] (default: 0x07).
0x0546 [7:1] Reserved Default: 0x00.
0 Integer Part N1 DPLL integer feedback divider, Bit 16 (default: 0b).
Default for Register 0x0544 to Register 0x0546: 0x007CB (which equals N1 = 1996).
Table 126. DPLL_1 REFC Fractional Part of Fractional Feedback Divider FRAC1
Address
Bits
Bit Name
Description
0x0547 [7:0] Digital PLL fractional
feedback divider—FRAC1
The numerator of the fractional-N feedback divider, Bits[7:0] (default: 0x04)
0x0548 [7:0] The numerator of the fractional-N feedback divider, Bits[15:8] (default: 0x00)
0x0549 [6:0] The numerator of the fractional-N feedback divider, Bits[22:16] (default: 0x00)
7 Reserved Default: 0b