Datasheet

AD9559 Data Sheet
Rev. C | Page 94 of 120
PLL_1 OUTPUT SYNC AND CLOCK DISTRIBUTION (REGISTER 0x0524 TO REGISTER 0x052E)
Table 117. APLL_1 P1 Divider Settings
Address Bits Bit Name Description
0x0524
[7:4]
Reserved
Default: 0x0
[3:0] P1 divider divide ratio 0000/0001 = 3
0010 = 4
0011 = 5
0100 = 6 (default)
0101 = 7
0110 = 8
0111 = 9
1000 = 10
1001 = 11
Table 118. Distribution Output Synchronization Settings
Address Bits Bit Name Description
0x0525 [7:3] Reserved Default: 00000b.
2 Sync source selection Selects the sync source for the clock distribution output channels.
0 (default) = direct.
1 = active reference.
[1:0]
Automatic sync mode
Automatic sync mode.
00 (default) = disabled.
01 = sync on DPLL frequency lock.
10 = sync on DPLL phase lock.
11 = reserved.
0x0526 [7:3] Reserved Default: 00000b.
2 APLL_1 locked
controlled sync disable
0 (default) = the clock distribution SYNC function is not enabled until APLL_1 has been
calibrated and is locked. After APLL calibration and lock, the output clock distribution sync is
armed, and the SYNC function for the clock outputs is under the control of Register 0x0525.
1 = overrides the lock detector state of the APLL; allows Register 0x0525 to control the output
SYNC function regardless of the APLL lock status.
1 Mask OUT1B sync Masks the synchronous reset to the OUT1B divider.
0 (default) = unmasked.
1 = masked. Setting this bit asynchronously releases the OUT1B divider from the static SYNC
state, thus allowing the OUT1B divider to toggle. OUT1B ignores all SYNC events while this bit
is set. Setting this bit does not enable the output drivers connected to this channel.
0 Mask OUT1A sync Masks the synchronous reset to the OUT1A divider.
0 (default) = unmasked.
1 = masked. Setting this bit asynchronously releases the OUT1A divider from the static SYNC
state, thus allowing the OUT1A divider to toggle. OUT1A ignores all SYNC events while this bit
is set. Setting this bit does not enable the output drivers connected to this channel.