Datasheet

Data Sheet AD9559
Rev. C | Page 9 of 120
Parameter Min Typ Max Unit Test Conditions/Comments
Rise/Fall Time (20% to 80%)
1
1.8 V Mode 1.5 3 ns 10 pF load
3.3 V Strong Mode 0.4 0.6 ns 10 pF load
3.3 V Weak Mode 8 ns 10 pF load
Duty Cycle
1.8 V Mode 50 % 10 pF load
3.3 V Strong Mode 47 51 56 % 10 pF load
3.3 V Weak Mode 51 % 10 pF load
Output Voltage High (V
OH
) Output driver static; strong drive strength
VDD3 = 3.3 V, I
OH
= 10 mA VDD3 − 0.3 V
VDD3 = 3.3 V, I
OH
= 1 mA VDD3 − 0.1 V
VDD3 = 1.8 V, I
OH
= 1 mA VDD − 0.2 V
Output Voltage Low (V
OL
) Output driver static; strong drive strength
VDD3 = 3.3 V, I
OL
= 10 mA 0.3 V
VDD3 = 3.3 V, I
OL
= 1 mA 0.1 V
VDD3 = 1.8 V, I
OL
= 1 mA 0.1 V
OUTPUT TIMING SKEW 10 pF load
Between OUT0A,
OUT0A
and OUT0B,
OUT0B
or OUT1A,
OUT1A
and OUT1B,
OUT1B
116 265 ps HSTL mode on both drivers; rising edge only;
any divide value
Additional Delay on One Driver by
Changing Its Logic Type
HSTL to LVDS 0 +15 +35 ps Positive value indicates that the LVDS edge is
delayed relative to HSTL
HSTL to 1.8 V CMOS −5 0 +5 ps Positive value indicates that the CMOS edge is
delayed relative to HSTL
OUT0B,
OUT0B
HSTL to OUT0B,
OUT0B
3.3 V CMOS, Strong Mode
−765 −280 +250 ns The CMOS edge is delayed relative to HSTL
OUT1B,
OUT1B
HSTL to OUT1B,
OUT1B
3.3 V CMOS, Strong Mode
−765 −280 +250 ns The CMOS edge is delayed relative to HSTL
1
The listed values are for the slower edge (rising or falling).