Datasheet
Data Sheet AD9559
Rev. C | Page 87 of 120
Table 87. Q0B_B Divider Setting
Address Bits Bit Name Description
0x042C [7:0] Q0_B divider 10-bit channel divider, Bits[7:0] (LSB).
Division equals channel divider, Bits[9:0] + 1.
([9:0] = 0 is divide-by-1, [9:0] = 1 is divide-by-2…[9:0] = 1023 is divide-by-1024).
0x042D [7:2] Reserved Default: 000000b.
[1:0] Q0_B divider 10-bit channel divider, Bits[9:8] (MSB), Bits[1:0].
0x042E [7:6] Reserved Default: 00b.
[5:0] Q0_B divider phase Divider initial phase after sync relative to the divider input clock (from the P0 divider output).
LSB is ½ of a period of the divider input clock.
Phase = 0 is no phase offset.
Phase = 1 is ½ a period offset.
DPLL_0 SETTINGS FOR REFERENCE INPUT A (REFA) (REGISTER 0x0440 TO REGISTER 0x044C)
Table 88. DPLL_0 REFA Priority Setting
Address Bits Bit Name Description
0x0440 [7:3] Reserved Default: 00000b
[2:1] REFA priority These bits set the priority level (0 to 3) of REFA relative to the other input references.
00 (default) = 0 (highest).
01 = 1.
10 = 2.
11 = 3.
0 Enable REFA This bit enables DPLL_0 to lock to REFA.
0 = REFA is not enabled for use by DPLL_0.
1 (default) = REFA is enabled for use by DPLL_0.
Table 89. DPLL_0 REFA Loop BW Scaling Factor
Address Bits Bit Name Description
0x0441 [7:0] DPLL loop BW scaling
factor (unit of 0.1 Hz)
Digital PLL loop bandwidth scaling factor, Bits[7:0] (default: 0xF4).
0x0442
[7:0]
Digital PLL loop bandwidth scaling factor, Bits[15:8] (default: 0x01).
The default for Register 0x0441 and Register 0x0442 = 0x01F4 = 500 (50 Hz loop BW).
The loop bandwidth should always be less than the DPLL phase detector frequency divided
by 20. The DPLL may not lock reliably if the DPLL loop BW is <50 Hz and a crystal is used for
the system clock. See the Choosing the SYSCLK Source section for details.
0x0443 [7:2] Reserved Default: 0x00.
1 Base loop filter
selection
0 = base loop filter with normal (70°) phase margin (default).
1 = base loop filter with high phase margin.
(≤0.1 dB peaking in the closed-loop transfer function for loop BW ≤ 2 kHz. Setting this bit is
also recommended for loop BW > 2 kHz.)
0 Reserved Default: 0b.
Table 90. DPLL_0 REFA Integer Part of Feedback Divider
Address Bits Bit Name Description
0x0444 [7:0] Integer Part N0 DPLL integer feedback divider (minus 1), Bits[7:0] (default: 0xCB)
0x0445 [7:0] DPLL integer feedback divider, Bits[15:8] (default: 0x07)
0x0446 [7:1] Reserved Default: 0x00
0 Integer Part N0 DPLL integer feedback divider, Bit 16 (default: 0b)
Default for Register 0x0444 to Register 0x0446: 0x007CB (which equals N1 = 1996)
Table 91. DPLL_0 REFA Fractional Part of Fractional Feedback Divider FRAC0
Address Bits Bit Name Description
0x0447 [7:0] Digital PLL fractional
feedback divider
—
FRAC0
The numerator of the fractional-N feedback divider, Bits[7:0] (default: 0x04)
0x0448 [7:0] The numerator of the fractional-N feedback divider, Bits[15:8] (default: 0x00)
0x0449 [6:0] The numerator of the fractional-N feedback divider, Bits[22:16] (default: 0x00)
7 Reserved Default: 0b