Datasheet

Data Sheet AD9559
Rev. C | Page 85 of 120
PLL_0 OUTPUT SYNC AND CLOCK DISTRIBUTION (REGISTER 0x0424 TO REGISTER 0x042E)
Table 82. APLL_0 P0 Divider Settings
Address Bits Bit Name Description
0x0424
[7:4]
Reserved
Default: 0x0
[3:0] P0 divider divide ratio 0000/0001 = 3
0010 = 4
0011 = 5
0100 = 6 (default)
0101 = 7
0110 = 8
0111 = 9
1000 = 10
1001 = 11
Table 83. Distribution Output Synchronization Settings
Address Bits Bit Name Description
0x0425 [7:3] Reserved Default: 00000b
2 Sync source selection Selects the sync source for the clock distribution output channels.
0 (default) = direct.
1 = active reference.
[1:0]
Automatic sync mode
Auto sync mode.
00 = (default) disabled.
01 = sync on DPLL frequency lock.
10 = sync on DPLL phase lock.
11 = reserved.
0x0426 [7:3] Reserved Reserved.
2 APLL_0 locked controlled
sync disable
0 (default) = the clock distribution SYNC function is not enabled until the APLL has
been calibrated and is locked. After APLL calibration and lock, the output clock
distribution sync is armed, and the SYNC function for the clock outputs is under the
control of Register 0x0425.
1 = overrides the lock detector state of the APLL; allows Register 0x0425 to control the
output SYNC function regardless of the APLL lock status.
1 Mask OUT0B sync Masks the synchronous reset to the OUT0B divider.
0 (default) = unmasked.
1 = masked. Setting this bit asynchronously releases the OUT0B divider from static sync
state, thus allowing the OUT0B divider to toggle. OUT0B ignores all sync events while
this bit is set. Setting this bit does not enable the output drivers connected to this channel.
0 Mask OUT0A sync Masks the synchronous reset to the OUT0A divider.
0 (default) = unmasked.
1 = masked. Setting this bit asynchronously releases the OUT0A divider from static sync
state, thus allowing the OUT0A divider to toggle. OUT0A ignores all sync events while
this bit is set. Setting this bit does not enable the output drivers connected to this channel.