Datasheet

Data Sheet AD9559
Rev. C | Page 83 of 120
Table 76. DPLL_0 History Accumulation Timer
Address Bits Bit Name Description
0x040B [7:0] History accumulation timer
(expressed in units of ms)
History accumulation timer, Bits[7:0].
Default: 0x0A. For Register 0x040B and Register 0x040C, 0x000A = 10 ms.
Maximum: 65 sec. This register controls the amount of tuning word averaging used to
determine the tuning word used in holdover. Never program a timer value of 0.
Default value: 0x000A = 10 (10 ms).
0x040C [7:0] History accumulation timer, Bits[15:8].
Default: 0x00.
Table 77. DPLL_0 History Mode
Address Bits Bit Name Description
0x040D [7:5] Reserved Reserved.
4 Single sample fallback
Controls holdover history. If tuning word history is not available for the reference that was
active just prior to holdover, then:
0 (default) = uses the free running frequency tuning word register value.
1 = uses the last tuning word from the DPLL.
3
Persistent history
Controls holdover history initialization. When switching to a new reference:
0 (default) = clears the tuning word history.
1 = retains the previous tuning word history.
[2:0] Incremental average History mode value from 0 to 7 (default: 0).
When set to nonzero, causes the first history accumulation to update prior to the first
complete averaging period. After the first full interval, updates occur only at the full period.
0 (default) = update only after the full interval has elapsed.
1 = update at 1/2 the full interval.
2 = update at 1/4 and 1/2 of the full interval.
3 = update at 1/8, 1/4, and 1/2 of the full interval.
…
7 = update at 1/256, 1/128, 1/64, 1/32, 1/16, 1/8, 1/4, and 1/2 of the full interval.
Table 78. DPLL_0 Fixed Closed Loop Phase Offset
Address Bits Bit Name Description
0x040E [7:0] Fixed phase offset
(signed; ps)
Fixed phase offset, Bits[7:0]
Default: 0x00
0x040F [7:0] Fixed phase offset, Bits[15:8]
Default 0x00
0x0410 [7:0] Fixed phase offset, Bits[23:16]
Default: 0x00
0x0411 [7:6] Reserved Reserved; default: 0x0
[5:0] Fixed phase offset
(signed; ps)
Fixed phase offset, Bits[29:24]
Default: 0x00
Table 79. DPLL_0 Incremental Closed-Loop Phase Offset Step Size
1
Address Bits Bit Name Description
0x0412 [7:0] Incremental phase offset
step size (ps)
Incremental phase offset step size, Bits[7:0]. Default: 0x00.
This register controls the static phase offset of the DPLL while it is locked.
0x0413 [7:0] Incremental phase offset step size, Bits[15:8]. Default: 0x00.
This register controls the static phase offset of the DPLL while it is locked.
1
Note that the default incremental closed loop phase lock offset step size value is 0x0000 = 0 (0 ns).
Table 80. DPLL_0 Phase Slew Rate Limit
Address Bits Bit Name Description
0x0414 [7:0] Phase slew rate limit
(µs/sec)
Phase slew rate limit, Bits[7:0].
Default: 0x00.
This register controls the maximum allowable phase slewing during phase adjustment.
(The phase adjustment controls are in Register 0x040E to Register 0x0411.)
Default phase slew rate limit: 0, or disabled. Minimum useful value is 310 µs/sec.
0x0415 [7:0] Phase slew rate limit, Bits[15:8].
Default = 0x00