Datasheet

AD9559 Data Sheet
Rev. C | Page 80 of 120
Table 62. REFC 20-bit DPLL R Divider
Address Bits Bit Name Description
0x0341 [7:0] R divider DPLL integer reference divider (minus 1), Bits[7:0] (default: 0xCF)
0x0342
[7:0]
DPLL integer reference divider (minus 1), Bits[15:8] (default: 0x00)
0x0343 [7:4] Reserved Default: 0x0
[3:0] R divider DPLL integer reference divider (minus 1), Bits[19:16] (default: 0x0)
Table 63. Nominal Period of REFC Input Clock
Address Bits Bit Name Description
0x0344 [7:0] REFC nominal
reference period (fs)
Nominal reference period, Bits[7:0] (default: 0xC9)
0x0345 [7:0] Nominal reference period, Bits[15:8] (default: 0xEA)
0x0346 [7:0] Nominal reference period, Bits[23:16] (default: 0x10)
0x0347 [7:0] Nominal reference period, Bits[31:24] (default: 0x03)
0x0348 [7:0] Nominal reference period, Bits[39:32] (default: 0x00)
Default for Register 0x0344 to Register 0x0348: 0x000310EAC9 = 51.44 ns (1/19.44 MHz)
Table 64. REFC Frequency Tolerance
Address Bits Bit Name Description
0x0349 [7:0] Inner tolerance Input reference frequency monitor inner tolerance, Bits[7:0] (default: 0x14).
0x034A [7:0] Input reference frequency monitor inner tolerance, Bits[15:8] (default: 0x00).
0x034B
[7:4]
Reserved
Default: 0x0.
[3:0] Inner tolerance Input reference frequency monitor inner tolerance, Bits[19:16].
Default for Register 0x0349 to Register 0x034B: 0x000014 = 20 (5% or 50,000 ppm).
The Stratum 3 clock requires inner tolerance of ±9.2 ppm and outer tolerance of ±12 ppm;
an SMC clock requires outer tolerance of ±48 ppm.
The allowable range for the inner tolerance is 0x00A (10%) to 0x8FF (2 ppm).
0x034C [7:0] Outer tolerance Input reference frequency monitor outer tolerance, Bits [7:0] (default: 0x0A).
0x034D [7:0] Input reference frequency monitor outer tolerance, Bits[15:8] (default: 0x00).
0x034E [7:4] Reserved Default: 0x0.
[3:0] Outer tolerance Input reference frequency monitor outer tolerance, Bits[19:16].
Default for Register 0x034C to Register 0x034E: 0x00000A = 10 (10% or 100,000 ppm).
The Stratum 3 clock requires inner tolerance of ±9.2 ppm and outer tolerance of ±12 ppm;
an SMC clock requires outer tolerance of ±48 ppm. The outer tolerance must be greater
than the inner tolerance so that there is hysteresis.
Table 65. REFC Validation Timer
Address
Bits
Bit Name
Description
0x034F [7:0] Validation timer (ms) Validation timer, Bits[7:0] (default: 0x0A).
This is the amount of time a reference input must be valid before it is declared valid by
the reference input monitor (default: 10 ms).
0x0350
[7:0]
Validation timer, Bits[15:8] (default: 0x00).
Table 66. REFC Lock Detectors
Address Bits Bit Name Description
0x0351 [7:0] Phase lock threshold Phase lock threshold, Bits[7:0] (default: 0xBC); default of 0x02BC = 700 ps
0x0352 [7:0] Phase lock threshold, Bits[15:8] (default: 0x02)
0x0353 [7:0] Phase lock threshold, Bits[23:16] (default: 0x00)
0x0354 [7:0] Phase lock fill rate Phase lock fill rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle)
0x0355 [7:0] Phase lock drain rate Phase lock drain rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle)
0x0356 [7:0] Frequency lock threshold Frequency lock threshold, Bits[7:0] (default: 0xBC); default of 0x02BC = 700 ps
0x0357 [7:0] Frequency lock threshold, Bits[15:8] (default: 0x02)
0x0358
[7:0]
Frequency lock threshold, Bits[23:16] (default: 0x00)
0x0359 [7:0] Frequency lock fill rate Frequency lock fill rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle)
0x035A [7:0] Frequency lock drain rate Frequency lock drain rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle)