Datasheet

Data Sheet AD9559
Rev. C | Page 79 of 120
Table 58. REFB Frequency Tolerance
Address Bits Bit Name Description
0x0329 [7:0] Inner tolerance Input reference frequency monitor inner tolerance, Bits[7:0] (default: 0x14)
0x032A [7:0] Input reference frequency monitor inner tolerance, Bits[15:8] (default: 0x00)
0x032B [7:4] Reserved Default: 0x0
[3:0] Inner tolerance Input reference frequency monitor inner tolerance, Bits[19:16].
Default for Register 0x0329 to Register 0x032B: 0x000014 = 20 (5% or 50,000 ppm).
The Stratum 3 clock requires inner tolerance of ±9.2 ppm and outer tolerance of ±12 ppm;
an SMC clock requires outer tolerance of ±48 ppm.
The allowable range for the inner tolerance is 0x00A (10%) to 0x8FF (2 ppm).
0x032C [7:0] Outer tolerance Input reference frequency monitor outer tolerance, Bits[7:0] (default: 0x0A).
0x032D [7:0] Input reference frequency monitor outer tolerance, Bits[15:8] (default: 0x00).
0x032E [7:4] Reserved Default: 0x0
[3:0] Outer tolerance Input reference frequency monitor outer tolerance, Bits[19:16].
Default for Register 0x032C to Register 0x032E: 0x00000A = 10 (10% or 100,000 ppm).
The Stratum 3 clock requires inner tolerance of ±9.2 ppm and outer tolerance of ±12 ppm;
an SMC clock requires outer tolerance of ±48 ppm. The outer tolerance must be greater
than the inner tolerance so that there is hysteresis.
Table 59. REFB Validation Timer
Address Bits Bit Name Description
0x032F [7:0] Validation timer (ms) Validation timer, Bits[7:0] (default: 0x0A).
This is the amount of time a reference input must be valid before it is declared valid by the
reference input monitor (default: 10 ms).
0x0330 [7:0] Validation timer, Bits[15:8] (default: 0x00).
Table 60. REFB Lock Detectors
Address Bits Bit Name Description
0x0331 [7:0] Phase lock threshold Phase lock threshold, Bits[7:0] (default: 0xBC); default of 0x02BC = 700 ps
0x0332 [7:0] Phase lock threshold, Bits[15:8] (default: 0x02)
0x0333 [7:0] Phase lock threshold, Bits[23:16] (default: 0x00)
0x0334 [7:0] Phase lock fill rate Phase lock fill rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle)
0x0335 [7:0] Phase lock drain rate Phase lock drain rate, Bits[7:0] (default: 0x0A=10 code/PFD cycle)
0x0336 [7:0] Frequency lock threshold Frequency lock threshold, Bits[7:0] (default: 0xBC); default of 0x02BC = 700 ps
0x0337
[7:0]
Frequency lock threshold, Bits[15:8] (default: 0x02)
0x0338 [7:0] Frequency lock threshold, Bits[23:16] (default: 0x00)
0x0339 [7:0] Frequency lock fill rate Frequency lock fill rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle)
0x033A
[7:0]
Frequency lock drain rate
Frequency lock drain rate, Bits[7:0] (default: 0x0A = 10 code/PFD cycle)
REFERENCE INPUT C (REGISTER 0x0340 TO REGISTER 0x035A)
Table 61. REFC Logic Type
Address Bits Bit Name Description
0x0340 [7:4] Reserved Default: 0x0
3 Enable REFC divide-by-2 Enables the reference input divide-by-2 for REFC
0 = bypasses the divide-by-2 (default)
1 = enables the divide-by-2
2 Reserved Default: 0b
[1:0] REFC logic type Selects logic family for REFC input receiver; only the REFC pin is used in CMOS mode
00 (default) = differential
01 = 1.2 V to 1.5 V CMOS
10 = 1.8 V to 2.5 V CMOS
11 = 3.0 V to 3.3 V CMOS