Datasheet

AD9559 Data Sheet
Rev. C | Page 76 of 120
SYSTEM CLOCK (REGISTER 0x0200 TO REGISTER 0x0207)
Table 45. System Clock PLL Feedback Divider (K Divider) and Configuration
Address Bits Bit Name Description
0x0200
[7:0]
System clock K divider
System clock PLL feedback divider value = 4 ≤ K ≤ 255 (default: 0x08).
Table 46. SYSCLK Configuration
Address Bits Bit Name Description
0x0201 [7:4] Reserved Reserved.
4 SYSCLK XTAL enable Enables the crystal maintaining amplifier for the system clock input.
1 (default) = crystal mode (crystal maintaining amplifier enabled).
0 = external crystal oscillator or other system clock source.
[2:1] SYSCLK J1 divider System clock input divider.
00 (default) = 1.
01 = 2.
10 = 4.
11 = 8.
0 SYSCLK doubler enable
(J0 divider)
Enables the clock doubler on system clock input to reduce noise. Setting this bit
may prevent the SYSCLK PLL from locking if the input duty cycle is not close
enough to 50%. See Table 4 for the limits on duty cycle.
0 = disable.
1 (default) = enable.
Table 47. Nominal System Clock Period
Address Bits Bit Name Description
0x0202 [7:0] Nominal system clock period (fs) System clock period, Bits[7:0]. This is the period of the system clock.
Default: 0x0E. [The default of 0x13670E = 1.271566 ns = 16 × (1/49.152 MHz).]
0x0203 [7:0] System clock period, Bits[15:8].
Default: 0x67.
0x0204 [7:5] Reserved Default: 0x13.
[4:0] Nominal system clock period (fs) System clock period, Bits[20:16].
Default: 0x13.
Table 48. System Clock Stability Period
Address
Bits
Bit Name
Description
0x0205 [7:0] System clock stability period (ms) System clock period, Bits[7:0]. The system clock stability period is the amount of
time that the system clock PLL must be locked before it is declared stable. The system
clock stability timer is reset automatically if the user writes to this register. The
system clock stability timer restarts on the next IO_UPDATE (Register 0x0005 = 0x01).
Default: 0x32 (0x000032 = 50 ms).
0x0206 [7:0] System clock period, Bits[15:8]. The system clock stability timer is reset
automatically if the user writes to this register. The system clock stability timer
restarts on the next IO_UPDATE (Register 0x0005 = 0x01).
Default: 0x00.
0x0207 [7:5] Reserved Default: 0x0.
[3:0] System clock stability period System clock period, Bits[19:16]. The system clock stability timer is reset
automatically if the user writes to this register. The system clock stability timer
restarts on the next IO_UPDATE (Register 0x0005 = 0x01).
Default: 0x0.