Datasheet
Data Sheet AD9559
Rev. C | Page 75 of 120
Table 43. IRQ Mask for the Digital PLL0 (DPLL_0)
Address Bits Bit Name Description
0x010D 7 Frequency unclamped Enables IRQ to indicate that DPLL_0 has exited a frequency clamped state
6
Frequency clamped
Enables IRQ to indicate that DPLL_0 has entered a frequency clamped state
5 Phase slew unlimited Enables IRQ to indicate that DPLL_0 has exited a phase slew limited state
4 Phase slew limited Enables IRQ to indicate that DPLL_0 has entered a phase slew limited state
3 Frequency unlocked Enables IRQ to indicate that DPLL_0 has lost frequency lock
2 Frequency locked Enables IRQ to indicate that DPLL_0 has acquired frequency lock
1 Phase unlocked Enables IRQ to indicate that DPLL_0 has lost phase lock
0 Phase locked Enables IRQ to indicate that DPLL_0 has acquired phase lock
0x010E 7 Switching Enables IRQ to indicate that DPLL_0 is switching to a new reference
6 Free run Enables IRQ to indicate that DPLL_0 has entered free run mode
5 Holdover Enables IRQ to indicate that DPLL_0 has entered holdover mode
4
History updated
Enables IRQ to indicate that DPLL_0 has updated its tuning word history
3 REFD activated Enables IRQ to indicate that DPLL_0 has activated REFD
2 REFC activated Enables IRQ to indicate that DPLL_0 has activated REFC
1 REFB activated Enables IRQ to indicate that DPLL_0 has activated REFB
0 REFA activated Enables IRQ to indicate that DPLL_0 has activated REFA
0x010F [7:5] Reserved Reserved
4 Sync clock distribution Enables IRQ for indicating a distribution sync event
3 APLL_0 unlocked Enables IRQ for APLL_0 unlocked
2 APLL_0 locked Enables IRQ for APLL_0 locked
1
APLL_0 cal complete
Enables IRQ for APLL_0 calibration complete
0 APLL_0 cal started Enables IRQ for APLL_0 calibration started
Table 44. IRQ Mask for the Digital PLL1 (DPLL_1)
Address Bits Bit Name Description
0x0110 7 Frequency unclamped Enables IRQ to indicate that DPLL_1 has exited a frequency clamped state
6 Frequency clamped Enables IRQ to indicate that DPLL_1 has entered a frequency clamped state
5 Phase slew unlimited Enables IRQ to indicate that DPLL_1 has exited a phase slew limited state
4 Phase slew limited Enables IRQ to indicate that DPLL_1 has entered a phase slew limited state
3 Frequency unlocked Enables IRQ to indicate that DPLL_1 has lost frequency lock
2 Frequency locked Enables IRQ to indicate that DPLL_1 has acquired frequency lock
1
Phase unlocked
Enables IRQ to indicate that DPLL_1 has lost phase lock
0 Phase locked Enables IRQ to indicate that DPLL_1 has acquired phase lock
0x0111 7 Switching Enables IRQ to indicate that DPLL_1 is switching to a new reference
6 Free run Enables IRQ to indicate that DPLL_1 has entered free run mode
5 Holdover Enables IRQ to indicate that DPLL_1 has entered holdover mode
4 History updated Enables IRQ to indicate that DPLL_1 has updated its tuning word history
3 REFD activated Enables IRQ to indicate that DPLL_1 has activated REFD
2 REFC activated Enables IRQ to indicate that DPLL_1 has activated REFC
1 REFB activated Enables IRQ to indicate that DPLL_1 has activated REFB
0 REFA activated Enables IRQ to indicate that DPLL_1 has activated REFA
0x0112 [7:5] Reserved Reserved
4 Sync clock distribution Enables IRQ for indicating a distribution sync event
3
APLL_1 unlocked
Enables IRQ for APLL_1 unlocked
2 APLL_1 locked Enables IRQ for APLL_1 locked
1 APLL_1 cal complete Enables IRQ for APLL_1 calibration complete
0 APLL_1 cal started Enables IRQ for APLL_1 calibration started