Datasheet

AD9559 Data Sheet
Rev. C | Page 72 of 120
REGISTER MAP BIT DESCRIPTIONS
SERIAL CONTROL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0005)
Table 35. Serial Configuration (Note that the contents of Register 0x0000 are not stored to the EEPROM.)
Address Bits Bit Name Description
0x0000 7 SDO enable Enables SPI port SDO pin.
1 = 4-wire (SDO pin enabled).
0 (default) = 3-wire.
6 LSB first/increment address Bit order for SPI port.
1 = least significant bit and byte first.
Register addresses are automatically incremented in multibyte transfers.
0 (default) = most significant bit and byte first.
Register addresses are automatically decremented in multibyte transfers.
5 Soft reset Device reset (invokes an EEPROM download if EEPROM or pin program is enabled.)
See the EEPROM and Pin Configuration and Function Descriptions sections for details.
[4:0] Reserved Default: 0x00.
Table 36. Readback Control
Address
Bits
Bit Name
Description
0x0004 [7:5] Reserved Default: 0x00.
4 Reset sans reg map Resets the part while maintaining the current register settings.
1 = resets the device.
0 (default) = no action.
3 Disable auto actions Disables the automatic updating of DPLL parameters.
1 = disables the automatic register write detection functions described in Table 32.
0 (default) = the live registers in the DPLL profile registers update immediately.
2 Reserved Default: 0x00.
1 2-wire SPI Enables 2-wire SPI mode, in which the
CS
pin state is ignored. Note that the
CS
stalled
high function is not available in this mode and that the correct number of clock edges
must be present on the SCLK pin during a transfer.
1 = ignores the state of the
CS
pin, making the M5/
CS
pin available as an M pin for
control/status of the
AD9559.
0 (default) = normal SPI operation.
0 Read buffer register For buffered registers, serial port readback reads from actual (active) registers instead of
the buffer.
1 = reads buffered values that take effect on next assertion of IO_UPDATE.
0 (default) = reads values currently applied to the device’s internal logic.
Table 37. Soft IO_UPDATE
Address Bits Bit Name Description
0x0005 [7:1] Reserved Reserved.
0 IO_UPDATE Writing a 1 to this bit transfers the data in the serial I/O buffer registers to the device’s
internal control registers. This is an autoclearing bit.
CLOCK PART FAMILY ID (REGISTER 0x000C AND REGISTER 0x000D)
Table 38. Clock Part Family ID
Address Bits Bit Name Description
0x000C [7:0] Clock part family ID, Bits[7:0] The values in this read-only register and Register 0x000D uniquely identify the AD9559.
This is useful in cases where the user’s software must determine which device is located
at a given I²C address.
Default: 0x02 for the AD9559.
0x000D [7:0] Clock part family ID, Bits[15:8] Default: 0x00 for the AD9559.