Datasheet

AD9559 Data Sheet
Rev. C | Page 66 of 120
Reg
Addr
(Hex)
Opt Name D7 D6 D5 D4 D3 D2 D1 D0
Def
(Hex)
0x054A W2 DPLL_1
fractional
feedback
divider
modulus
(23 bits)
Digital PLL_1 feedback divider modulus—MOD1, Bits[7:0] 0x05
0x054B W2 Digital PLL_1 feedback divider modulus—MOD1, Bits[15:8] 0x00
0x054C W2 Reserved Digital PLL_1 feedback divider modulus—MOD1, Bits[22:16] 0x00
DPLL_1 Settings for Reference Input D
0x054D Reference
priority
Reserved REFD priority, Bits[1:0] Enable
REFD
0x01
0x054E W2 DPLL_1
loop BW
(16 bits)
Digital PLL_1 loop BW scaling factor, Bits[7:0] (default: 0x01F4 = 50 Hz) 0xF4
0x054F W2 Digital PLL_1 loop BW scaling factor, Bits[15:8] 0x01
0x0550 W2 Reserved Base filter Reserved 0x00
0x0551 W2 DPLL_1
N1 divider
(17 bits)
Digital PLL_1 feedback divider—Integer Part N1, Bits[7:0] 0xCB
0x0552 W2 Digital PLL_1 feedback divider—Integer Part N1, Bits[15:8] 0x07
0x0553 W2 Reserved Digital
PLL
feedback
divider—
Integer
Part N1,
Bit 16
0x00
0x0554 DPLL_1
fractional
feedback
divider
(23 bits)
Digital PLL_1 fractional feedback divider—FRAC1, Bits[7:0] 0x04
0x0555 Digital PLL_1 fractional feedback divider—FRAC1, Bits[15:8] 0x00
0x0556 Reserved Digital PLL_1 fractional feedback divider—FRAC1, Bits[22:16] 0x00
0x0557 W2 DPLL_1
fractional
feedback
divider
modulus
(23 bits)
Digital PLL_1 feedback divider modulus—MOD1, Bits[7:0] 0x05
0x0558 W2 Digital PLL_1 feedback divider modulus—MOD1, Bits[15:8] 0x00
0x0559 W2 Reserved Digital PLL_1 feedback divider modulus—MOD1, Bits[22:16] 0x00
DPLL_1 Settings for Reference Input A
0x055A Reference
priority
Reserved REFA priority, Bits[1:0] Enable
REFA
0x00
0x055B W2 DPLL_1
loop BW
(16 bits)
Digital PLL_1 loop BW scaling factor, Bits[7:0] (default: 0x01F4 = 50 Hz) 0xF4
0x055C W2 Digital PLL_1 loop BW scaling factor, Bits[15:8] 0x01
0x055D W2 Reserved Base filter Reserved 0x00
0x055E W2 DPLL_1
N1 divider
(17 bits)
Digital PLL_1 feedback divider—Integer Part N1, Bits[7:0] 0xCB
0x055F W2 Digital PLL_1 feedback divider—Integer Part N1, Bits[15:8] 0x07
0x0560 W2 Reserved Digital
PLL
feedback
divider—
Integer
Part N1,
Bit 16
0x00
0x0561 DPLL_1
fractional
feedback
divider
(23 bits)
Digital PLL_1 fractional feedback divider—FRAC1, Bits[7:0] 0x04
0x0562 Digital PLL_1 fractional feedback divider—FRAC1, Bits[15:8] 0x00
0x0563 Reserved Digital PLL_1 fractional feedback divider—FRAC1, Bits[22:16] 0x00
0x0564
W2
DPLL_1
fractional
feedback
divider
modulus
(23 bits)
Digital PLL_1 feedback divider modulus—MOD1, Bits[7:0]
0x05
0x0565
W2
Digital PLL_1 feedback divider modulus—MOD1, Bits[15:8]
0x00
0x0566
W2
Reserved
Digital PLL_1 feedback divider modulus—MOD1, Bits[22:16]
0x00