Datasheet

Data Sheet AD9559
Rev. C | Page 59 of 120
REGISTER MAP
Register addresses that are not listed in Table 34 are not used, and writing to those registers has no effect. The user should write the
default value to sections of registers marked reserved. R = read only. A = autoclear. E = excluded from EEPROM loading. W1, W2, W5,
W6, and W7 = write detection (see Table 32 for more information). L = live (IO_UPDATE not required for register to take effect or for
a read-only register to be updated.)
Table 34.
Reg
Addr
(Hex) Opt Name D7 D6 D5 D4 D3 D2 D1 D0
Def
(Hex)
Serial Control Port and Part Identification
0x0000 L, E SPI control SDO enable LSB first/
increment
address
Soft reset Reserved 0x00
0x0000 L I²C control Reserved Soft reset Reserved 0x00
0x0004 Readback
control
Reserved Reset sans
reg map
Disable
auto actions
Reserved 2-wire SPI Read
buffer
register
0x00
0x0005 A, L IO_UPDATE Reserved IO_
UPDATE
0x00
0x000A R, L Reserved 0x12
0x000B R, L Reserved 0x0F
0x000C R, L Part family
ID
Clock part family ID, Bits[7:0] 0x02
0x000D R, L Clock part family ID, Bits[15:8] 0x00
0x000E L User
scratchpad
User scratchpad, Bits[7:0] 0x00
0x000F L User scratchpad, Bits[15:8] 0x00
General Configuration
0x0100 M pin
drivers
M3 driver mode, Bits[1:0] M2 driver mode, Bits[1:0] M1 driver mode, Bits[1:0] M0 driver mode, Bits[1:0] 0x00
0x0101 Reserved M5 driver mode, Bits[1:0] M4 driver mode, Bits[1:0] 0x00
0x0102 W7 M0FUNC M0
output/
input
M0 function, Bits[6:0] 0x00
0x0103 W7 M1FUNC M1
output/
input
M1 function, Bits[6:0] 0x00
0x0104 W7 M2FUNC M2
output/
input
M2 function, Bits[6:0] 0x00
0x0105 W7 M3FUNC M3
output/
input
M3 function, Bits[6:0] 0x00
0x0106
W7
M4FUNC
M4
output/
input
M4 function, Bits[6:0]
0x00
0x0107 W7 M5FUNC M5
output/
input
M5 function, Bits[6:0] 0x00
0x0108 W5 Watchdog
timer
Watchdog timer (ms), Bits[7:0] 0x00
0x0109 W5 Watchdog timer (ms), Bits[15:8] 0x00
0x010A
IRQ mask
common
Reserved
SYSCLK
unlocked
SYSCLK
stable
SYSCLK
locked
Watchdog
timer
Reserved
EEPROM
fault
EEPROM
complete
0x00
0x010B Reserved REFB
validated
REFB fault
cleared
REFB fault Reserved REFA
validated
REFA fault
cleared
REFA fault 0x00
0x010C Reserved REFD
validated
REFD fault
cleared
REFD fault Reserved REFC
validated
REFC fault
cleared
REFC fault 0x00
0x010D IRQ mask
DPLL_0
Frequency
unclamped
Frequency
clamped
Phase slew
unlimited
Phase slew
limited
Frequency
unlocked
Frequency
locked
Phase
unlocked
Phase
locked
0x00
0x010E Switching Free run Holdover History
updated
REFD
activated
REFC
activated
REFB
activated
REFA
activated
0x00
0x010F Reserved Sync clock
distribution
APLL_0
unlocked
APLL_0
locked
APLL_0 cal
complete
APLL_0
cal started
0x00
0x0110 IRQ mask
DPLL_1
Frequency
unclamped
Frequency
clamped
Phase slew
unlimited
Phase slew
limited
Frequency
unlocked
Frequency
locked
Phase
unlocked
Phase
locked
0x00
0x0111
Switching
Free run
Holdover
History
updated
REFD
activated
REFC
activated
REFB
activated
REFA
activated
0x00
0x0112 Reserved Sync clock
distribution
APLL_1
unlocked
APLL_1
locked
APLL_1 cal
complete
APLL_1
cal started
0x00