Datasheet

AD9559 Data Sheet
Rev. C | Page 54 of 120
When all the data bytes are read or written, stop conditions are
established. In write mode, the master (transmitter) asserts a
stop condition to end data transfer during the 10
th
clock pulse
following the acknowledge bit for the last data byte from the slave
device (receiver). In read mode, the master device (receiver)
receives the last data byte from the slave device (transmitter) but
does not pull SDA low during the ninth clock pulse. This is known
as a nonacknowledge bit. By receiving the nonacknowledge bit,
the slave device knows that the data transfer is finished and enters
idle mode. The master then takes the data line low during the low
period before the 10
th
clock pulse, and high during the 10
th
clock
pulse to assert a stop condition.
A start condition can be used in place of a stop condition.
Furthermore, a start or stop condition can occur at any time, and
partially transferred bytes are discarded.
Figure 52. Start and Stop Conditions
Figure 53. Acknowledge Bit
Figure 54. Data Transfer Process (Master Write Mode, 2-Byte Transfer)
Figure 55. Data Transfer Process (Master Read Mode, 2-Byte Transfer)
SDA
START CONDITION
STOP CONDITION
SCL
S
P
10644-036
1 2
8 9
1 2
3 TO 73 TO 7 8 9
10
SDA
SCL
S
MSB
ACK FROM
SLAVE RECEIVER
ACK FROM
SLAVE RECEIVER
P
10644-037
1 2
8 9
1 2
3 TO 73 TO 7 8 9 10
ACK FROM
SLAVE RECEIVER
ACK FROM
SLAVE RECEIVER
SDA
SCL
S
MSB
P
10644-038
1
2
8 9
1 2
3 TO 73 TO 7 8 9 10
ACK FROM
MASTER RECEIVER
NONACK FROM
MASTER RECEIVER
SDA
SCL
S
P
10644-039