Datasheet

Data Sheet AD9559
Rev. C | Page 53 of 120
I²C SERIAL PORT OPERATION
The I
2
C interface has the advantage of requiring only two control
pins and is a de facto standard throughout the I
2
C industry.
However, its disadvantage is programming speed, which is 400 kbps
maximum. The AD9559 I²C port design is based on the I²C fast
mode standard; it supports both the 100 kHz standard mode and
400 kHz fast mode. Fast mode imposes a glitch tolerance
requirement on the control signals. That is, the input receivers
ignore pulses of less than 50 ns duration.
The AD9559 I²C port consists of a serial data line (SDA) and a
serial clock line (SCL). In an I²C bus system, the AD9559 is
connected to the serial bus (data bus SDA and clock bus SCL)
as a slave device; that is, no clock is generated by the AD9559.
The AD9559 uses direct 16-bit memory addressing instead of
traditional 8-bit memory addressing.
The AD9559 allows up to seven unique slave devices to occupy
the I
2
C bus. These are accessed via a 7-bit slave address
transmitted as part of an I
2
C packet. Only the device with a
matching slave address responds to subsequent I
2
C commands.
Table 25 lists the supported device slave addresses.
I
2
C Bus Characteristics
A summary of the various I
2
C abbreviations appears in Table 30.
Table 30. I
2
C Bus Abbreviation Definitions
Abbreviation Definition
S Start
Sr Repeated start
P Stop
A Acknowledge
A
Nonacknowledge
W
Write
R
Read
The transfer of data is shown in Figure 51. One clock pulse is
generated for each data bit transferred. The data on the SDA line
must be stable during the high period of the clock. The high or
low state of the data line can change only when the clock signal on
the SCL line is low.
Figure 51. Valid Bit Transfer
Start/stop functionality is shown in Figure 52. The start condition
is characterized by a high-to-low transition on the SDA line while
SCL is high. The start condition is always generated by the master
to initialize a data transfer. The stop condition is characterized by
a low-to-high transition on the SDA line while SCL is high. The
stop condition is always generated by the master to terminate
a data transfer. Every byte on the SDA line must be eight bits long.
Each byte must be followed by an acknowledge bit; bytes are sent
MSB first.
The acknowledge bit (A) is the ninth bit attached to any 8-bit data
byte. An acknowledge bit is always generated by the receiving device
(receiver) to inform the transmitter that the byte has been received.
It is done by pulling the SDA line low during the ninth clock pulse
after each 8-bit data byte.
The nonacknowledge bit (
A
) is the ninth bit attached to any 8-bit
data byte. A nonacknowledge bit is always generated by the
receiving device (receiver) to inform the transmitter that the byte
has not been received. It is done by leaving the SDA line high
during the ninth clock pulse after each 8-bit data byte.
Data Transfer Process
The master initiates data transfer by asserting a start condition.
This indicates that a data stream follows. All I²C slave devices
connected to the serial bus respond to the start condition.
The master then sends an 8-bit address byte over the SDA line,
consisting of a 7-bit slave address (MSB first) plus an R/
W
bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 = write,
1 = read).
The peripheral whose address corresponds to the transmitted address
responds by sending an acknowledge bit. All other devices on the
bus remain idle while the selected device waits for data to be read
from or written to it. If the R/
W
bit is 0, the master (transmitter)
writes to the slave device (receiver). If the R/
W
bit is 1, the master
(receiver) reads from the slave device (transmitter).
The format for these commands is described in the Data Transfer
Format section.
Data is then sent over the serial bus in the format of nine clock
pulses, one data byte (eight bits) from either master (write mode)
or slave (read mode) followed by an acknowledge bit from the
receiving device. The number of bytes that can be transmitted per
transfer is unrestricted. In write mode, the first two data bytes
immediately after the slave address byte are the internal memory
(control registers) address bytes, with the high address byte first.
This addressing scheme gives a memory address of up to 2
16
− 1 =
65,535. The data bytes after these two memory address bytes are
register data written to or read from the control registers. In read
mode, the data bytes after the slave address byte are register data
written to or read from the control registers.
DATA LINE
STABLE;
DATA VALID
CHANGE
OF DATA
ALLOWED
SDA
SCL
10644-049