Datasheet

Data Sheet AD9559
Rev. C | Page 49 of 120
SERIAL CONTROL PORT
The AD9559 serial control port is a flexible, synchronous serial
communications port that provides a convenient interface to
many industry-standard microcontrollers and microprocessors.
The AD9559 serial control port is compatible with most
synchronous transfer formats, including I²C, Motorola SPI, and
Intel SSR protocols. The serial control port allows read/write
access to the AD9559 register map.
In SPI mode, single or multiple byte transfers are supported.
The SPI port configuration is programmable via Register
0x0000. This register is integrated into the SPI control logic
rather than in the register map and is distinct from the I
2
C
Register 0x0000. It is also inaccessible to the EEPROM
controller.
Although the AD9559 supports both the SPI and I
2
C serial port
protocols, only one is active following power-up (as determined
by the M3, M4/SDO, and M5/
CS
multifunction pins during the
start-up sequence). That is, the only way to change the serial port
protocol is to reset the device (or cycle the device power supply).
SPI/I²C PORT SELECTION
Because the AD9559 supports both SPI and I²C protocols, the
active serial port protocol depends on the logic state of M3,
M4/SDO, and the M5/
CS
pins. See Table 25 for the I
2
C address
assignments. Note that there are no internal pull-up or pull-
down resistors on these pins.
Table 25. SPI/I²C Serial Port Setup
M5/
CS
M4/SDO M3 SPI/I²C Address
X
1
X
1
Low SPI
Low Low High I²C, 1101100 (0x6C)
Low
High
High
I²C, 1101101 (0x6D)
High Low High I²C, 1101110 (0x6E)
High High High I²C, 1101111 (0x6F)
1
X = Don’t care.
SPI SERIAL PORT OPERATION
Pin Descriptions
The SCLK (serial clock) pin serves as the serial shift clock. This
pin is an input. SCLK synchronizes serial control port read and
write operations. The rising edge SCLK registers write data bits,
and the falling edge registers read data bits. The SCLK pin
supports a maximum clock rate of 40 MHz.
The SDIO (serial data input/output) pin is a dual-purpose pin
and acts either as an input only (unidirectional mode) or as
both an input and an output (bidirectional mode). The AD9559
default SPI mode is bidirectional.
The SDO (serial data output) pin is useful only in unidirectional
I/O mode. It serves as the data output pin for read operations.
The
CS
(chip select) pin is an active low control that gates read
and write operations. This pin is internally connected to a 30 kΩ
pull-up resistor. When
CS
is high, the SDO and SDIO pins go
into a high impedance state.
SPI Mode Operation
The SPI port supports both 3-wire (bidirectional) and 4-wire
(unidirectional) hardware configurations and both MSB-first
and LSB-first data formats. Both the hardware configuration
and data format features are programmable. By default, the
AD9559 uses the bidirectional MSB-first mode. The reason that
bidirectional is the default mode is so that the user can still
write to the device, if it is wired for unidirectional operation, to
switch to unidirectional mode.
Assertion (active low) of the
CS
pin initiates a write or read
operation to the AD9559 SPI port. For data transfers of three
bytes or fewer (excluding the instruction word), the device
supports the
CS
stalled high mode. In this mode, the
CS
pin can
be temporarily deasserted on any byte boundary, allowing time
for the system controller to process the next byte.
CS
can be
deasserted only on byte boundaries, however. This applies to
both the instruction and data portions of the transfer.
During stall high periods, the serial control port state machine
enters a wait state until all data is sent. If the system controller
decides to abort a transfer midstream, the state machine must be
reset by either completing the transfer or by asserting the
CS
pin for at least one complete SCLK cycle (but less than eight
SCLK cycles). Deasserting the
CS
pin on a nonbyte boundary
terminates the serial transfer and flushes the buffer.
In the streaming mode (see Table 26), any number of data bytes
can be transferred in a continuous stream. The register address
is automatically incremented or decremented.
CS
must be
deasserted at the end of the last byte transferred, thereby ending
the stream mode.
Table 26. Byte Transfer Count
W1 W0 Bytes to Transfer
0 0 1
0 1 2
1 0 3
1 1 Streaming mode