Datasheet

AD9559 Data Sheet
Rev. C | Page 44 of 120
EEPROM Instructions
Table 22 lists the EEPROM controller instruction set. The
controller recognizes all instruction types whether it is in
upload or download mode, except for the pause instruction,
which is only recognizes in upload mode.
The IO_UPDATE, calibrate, distribution sync, and end instruct-
tions are, for the most part, self-explanatory. The others, however,
warrant further detail, as described in the following paragraphs.
Data instructions are those that have a value from 0x00 to 0x7F.
A data instruction tells the controller to transfer data between
the EEPROM and the register map. The controller needs the
following two parameters to carry out the data transfer:
• The number of bytes to transfer
• The register map target address
Table 22. EEPROM Controller Instruction Set
Instruction
Value (Hex) Instruction Type
Bytes
Needed Description
0x00 to 0x7F
Data
3
A data instruction tells the controller to transfer data to or from the device settings part
of the register map. A data instruction requires two additional bytes that, together,
indicate a starting address in the register map. Encoded in the data instruction is the
number of bytes to transfer, which is one more than the instruction value.
0x80 IO_UPDATE 1 The controller issues a soft IO_UPDATE (which is analogous to the user writing
Register 0x0005 = 0x01).
0x90 Calibrate both
APLLs
1 The controller initiates an APLL calibration sequence to both APLL_0 and APLL_1 while
downloading from the EEPROM. APLL calibration is gated by the system clock being stable.
0x91 Calibrate APLL_0 1 When the controller encounters this instruction while downloading from the EEPROM,
it initiates an APLL_0 calibration sequence. APLL calibration is gated by the system clock
being stable.
0x92
Calibrate APLL_1
1
When the controller encounters this instruction while downloading from the EEPROM,
it initiates an APLL_1 calibration sequence. APLL calibration is gated by the system clock
being stable.
0x98 Set User Free run
Mode (both PLLs)
1 When the controller encounters this instruction while downloading from the EEPROM,
it forces both of the DPLLs into user free run mode.
0x99 Set User Free run
Mode (DPLL_0)
1 When the controller encounters this instruction while downloading from the EEPROM,
it forces both of the DPLLs into user free run mode.
0x9A Set User Free run
Mode (DPLL_1)
1 When the controller encounters this instruction while downloading from the EEPROM,
it forces both of the DPLLs into user free run mode.
0xA0 Distribution sync
(all outputs)
1 When the controller encounters this instruction while downloading from the EEPROM,
it issues a sync pulse to the PLL0 and PLL1 channel dividers.
Note that the APLL_0 must be locked before the sync pulse reaches the PLL_0 channel
dividers, and APLL_1 must be locked before the sync pulse reaches the PLL_1 channel
dividers, unless overridden.
0xA1 Distribution sync
(PLL0 outputs)
1 When the controller encounters this instruction while downloading from the EEPROM, it
issues a sync pulse to the PLL_0 channel dividers.
Note that, unless overridden, this sync pulse is gated by the APLL_0 lock detect signal.
0xA2 Distribution sync
(PLL1 outputs)
1 When the controller encounters this instruction while downloading from the EEPROM,
it issues a sync pulse to the PLL1 channel dividers.
Note that, unless overridden, this sync pulse is gated by the APLL_1 lock detect signal.
0xB0 Clear condition 1 0xB0 is the null condition instruction (see the EEPROM Conditional Processing section).
0xB1 to 0xBF Condition 1 0xB1 to 0xBF are condition instructions and correspond to Condition 1 through
Condition 15, respectively (see the EEPROM Conditional Processing section).
0xFE Pause 1 When the controller encounters this instruction in the scratchpad while uploading to the
EEPROM, it resets the scratchpad address pointer and holds the EEPROM address pointer
at its last value. This allows storage of more than one instruction sequence in the
EEPROM. Note that the controller does not copy this instruction to the EEPROM during
upload.
0xFF End of data 1 When the controller encounters this instruction in the scratchpad while uploading to the
EEPROM, it resets both the scratchpad address pointer and the EEPROM address pointer
and then enters an idle state.
When the controller encounters this instruction while downloading from the EEPROM,
it resets the EEPROM address pointer and then enters an idle state.