Datasheet
Data Sheet AD9559
Rev. C | Page 43 of 120
All IRQ monitor register bits can be cleared by setting the clear all
IRQs bit in the IRQ register (Register 0x0A05). Note that the bits
in Register 0x0A05 are autoclearing. Setting Bit 0 results in the
deassertion of all IRQs. Alternatively, the user can program any of
the multifunction pins to clear all IRQs, which allows the user to
clear all IRQs by means of a hardware pin rather than by a serial
I/O port operation.
WATCHDOG TIMER
The watchdog timer is a general-purpose programmable timer.
To set the timeout period, the user writes to the 16-bit watchdog
timer register (Address 0x0108 to Address 0x0109). A value of
0x0000 in this register disables the timer. A nonzero value sets
the timeout period in milliseconds, giving the watchdog timer
a range of 1 ms to 65.535 sec. The relative accuracy of the timer
is approximately 0.1% with an uncertainty of 0.5 ms.
If enabled, the timer runs continuously and generates a timeout
event when the timeout period expires. The user has access
to the watchdog timer status via the IRQ mechanism and the
multifunction pins (M0 to M3). The M4 and M5 multifunction
pins are available if they are not used for the serial port. In the
case of the multifunction pins, the timeout event of the watchdog
timer is a pulse that lasts 32 system clock periods.
There are two ways to reset the watchdog timer (thereby preventing
it from causing a timeout event). The first method is to write a
Logic 1 to the autoclearing clear watchdog timer bit in the clear
IRQ groups register (Register 0x0A05, Bit 7). Alternatively, the
user can program any of the multifunction pins to reset the
watchdog timer. This allows the user to reset the timer by means
of a hardware pin rather than by a serial I/O port operation.
EEPROM
EEPROM Overview
The AD9559 contains an integrated 2048-byte, electrically
erasable, programmable read-only memory (EEPROM). The
AD9559 can be configured to perform a download at power-up
via the multifunction pins (M1 and M0), but uploads and
downloads can also be performed on demand via the EEPROM
control registers (Address 0x0E00 to Address 0x0E03).
The EEPROM provides the ability to upload and download
configuration settings to and from the register map. Figure 43
shows a functional diagram of the EEPROM.
Register 0x0E10 to Register 0x0E4F represent a 64-byte EEPROM
storage sequence area (referred to as the scratchpad in this
section) that enables the user to store a sequence of instructions
for transferring data to the EEPROM from the device settings
portion of the register map. Note that the default values for these
registers provide a sample sequence for saving/retrieving all of the
AD9559 EEPROM-accessible registers. Figure 43 shows the
connectivity between the EEPROM and the controller that
manages data transfer between the EEPROM and the register map.
The controller oversees the process of transferring EEPROM data
to and from the register map. There are two modes of operation
handled by the controller: saving data to the EEPROM (upload
mode) or retrieving data from the EEPROM (download mode).
In either case, the controller relies on a specific instruction set.
Figure 43. EEPROM Functional Diagram
EEPROM
(0x000
TO 0x7FF)
DATA
DATA
DATA
EEPROM
ADDRESS
POINTER
REGISTER MAP
DEVICE
SETTINGS
SCRATCH PAD
(0x0E10 TO 0x0E4F)
SERIAL
INPUT/OUTPUT
PORT
CONDITION
0x0E01[3:0]
EEPROM
CONTROLLER
M1
M0
DEVICE
SETTINGS
ADDRESS
POINTER
SCRATCH PAD
ADDRESS
POINTER
10644-024