Datasheet

AD9559 Data Sheet
Rev. C | Page 42 of 120
STATUS AND CONTROL
MULTIFUNCTION PINS (M0 TO M5)
The AD9559 has six digital CMOS I/O pins (M0 to M5) that are
configurable for a variety of uses. To use these functions, the user
must set them by writing to Register 0x0100 and Register 0x0101.
The function of these pins is programmable via the register map.
Each pin can control or monitor an assortment of internal
functions based on Register 0x0102 to Register 0x0107.
The M pins feature a special write detection logic that prevents
them from behaving unpredictably when their function changes.
When the when the user writes to these registers, the existing M
pin function stops. The new M pin function takes effect on the
next IO_UPDATE (Register 0x0005 = 0x01).
The M4 and M5 pins are multiplexed with serial port functions.
For the M4/SDO pin to function as M4, the AD9559 must not be
in 4-wire SPI mode. For the M5/
CS
pin to function as M5, either
I²C or 2-wire SPI mode must be in use.
The M pins operate in one of four modes: active high CMOS,
active low CMOS, open-drain PMOS, and open-drain NMOS.
00—Active high CMOS: The M pin is Logic 0 when deasserted and
Logic 1 when asserted. This is the default operating mode.
01—Active low CMOS: The M pin is Logic 1 when deasserted
and Logic 0 when asserted.
10—Open-drain PMOS: The M pin is high impedance when
deasserted and active high when asserted; it requires an
external pull-down resistor.
11—Open-drain NMOS: The M pin is high impedance when
deasserted and active low when asserted; it requires an
external pull-up resistor.
To monitor an internal function with a multifunction pin, write a
Logic 1 to the most significant bit of the register associated with
the desired multifunction pin. The value of the seven least
significant bits of the register defines the control function, as
shown in Table 196.
To control an internal function with a multifunction pin, write a
Logic 0 to the most significant bit of the register associated with
the desired multifunction pin. The monitored function depends
on the value of the seven least significant bits of the register, as
shown in Table 197.
If more than one multifunction pin operates on the same control
signal, internal priority logic ensures that only one multifunction
pin serves as the signal source. The selected pin is the one with
the lowest numeric suffix. For example, if both M0 and M3
operate on the same control signal, M0 is used as the signal
source and the redundant pins are ignored.
At power-up, the multifunction pins can force the device into
certain configurations as defined in the Multifunction Pins at
Reset/Power-Up section. This behavior is valid only during
power-up or following a reset, after which the pins can be
reconfigured via the serial programming port or via the EEPROM.
IRQ FUNCTION
The AD9559 IRQ function can be assigned to any M pin. There
are three IRQ categories: PLL0, PLL1, and common. This means
an M pin can be set to respond only to IRQs that relate to PLL0,
PLL1, or to common functions. An M pin can also be set to
respond to all IRQs.
The AD9559 asserts the IRQ pin when any bit in the IRQ monitor
register (Address 0x0D08 to Address 0x0D10) is a Logic 1. Each
bit in this register is associated with an internal function that is
capable of producing an interrupt. Furthermore, each bit of the
IRQ monitor register is the result of a logical AND of the associated
internal interrupt signal and the corresponding bit in the IRQ
mask register (Address 0x010A to Address 0x0112). That is, the
bits in the IRQ mask register have a one-to-one correspondence
with the bits in the IRQ monitor register. When an internal
function produces an interrupt signal and the associated IRQ mask
bit is set, the corresponding bit in the IRQ monitor register is set.
Be aware that clearing a bit in the IRQ mask register removes only
the mask associated with the internal interrupt signal. It does not
clear the corresponding bit in the IRQ monitor register.
The IRQ function is edge-triggered. This means that if the
condition that generated an IRQ (for example, loss of DPLL_0
lock) still exists after an IRQ is cleared, the IRQ does not reactivate
until DPLL_0 lock is restored and lost again. However, if the IRQs
are enabled when DPLL_0 is not locked, an IRQ is generated.
The IRQ function of an M pin is the result of a logical OR of all
the IRQ monitor register bits. The AD9559 asserts an IRQ as long
as any of the IRQ monitor register bits is a Logic 1. Note that it
is possible to have multiple bits set in the IRQ monitor register.
Therefore, when the AD9559 asserts an IRQ, it may indicate an
interrupt from several different internal functions. The IRQ
monitor register provides a way to interrogate the AD9559 to
determine which internal function(s) produced the interrupt.
Typically, when the AD9559 asserts an IRQ, the user interrogates
the IRQ monitor register to identify the source of the interrupt
request. After servicing an indicated interrupt, the user should
clear the associated IRQ monitor register bit via the IRQ clearing
register (Address 0x0A05 to Address 0x0A0E). The bits in the
IRQ clearing register have a one-to-one correspondence with
the bits in the IRQ monitor register.
Note that the IRQ clearing registers are autoclearing. The M pin
associated with an IRQ remains asserted until the user clears all of
the bits in the IRQ monitor register that indicate an interrupt.