Datasheet

Data Sheet AD9559
Rev. C | Page 41 of 120
The 3.3 V CMOS drivers feature a CMOS drive strength that
allows the user to choose between a strong, high performance
CMOS driver or a lower power setting with less EMI and
crosstalk. The best setting is application dependent.
• All outputs have an LVDS boost mode that provides
increased output amplitude in applications that require it.
• For applications where LVPECL levels are required, the
user should choose the HSTL mode and then ac-couple
the output signal. See the Input/Output Termination
Recommendations section for recommended termination
schemes.
CLOCK DISTRIBUTION SYNCHRONIZATION
Divider Synchronization
The dividers in the channels can be synchronized with each other.
At power-up, they are held static until a sync signal is initiated
through serial port, EEPROM event, DPLL locked sync, or
a reference edge-initiated sync. This provides time for program-
ming the dividers and for the DPLL to lock before the outputs are
enabled. A user-initiated sync signal can also be supplied to the
dividers at any time (as a manual synchronization) using an M pin.
A channel can be programmed to ignore the sync function.
When programmed to ignore the sync, the channel sync block
issues a sync pulse immediately, and the channel ignores all
other sync signals.
The digital logic triggers a sync event from one of the following
sources:
• Register programming through serial port
• EEPROM programming
• A multifunction pin configured for the SYNC signal
• Other automatic conditions determined by the DPLL
configuration: DPLL lock or feedback divider pulse