Datasheet

AD9559 Data Sheet
Rev. C | Page 40 of 120
CLOCK DISTRIBUTION
Figure 41. Clock Distribution Block Diagram from VCO_0
Figure 42. Clock Distribution Block Diagram from VCO_1
The AD9559 has two identical clock distribution sections: one
for PLL_0 from VCO_0 and the other for PLL_1. See Figure 41
for a diagram of the clock distribution block for PLL_0 and
Figure 42 for the PLL_1 block.
CLOCK DIVIDERS
P0 and P1 Dividers
The first block in each clock distribution section is the P divider.
The P divider divides the VCO output frequency down to a
maximum frequency of ≤1.25 GHz and has special circuitry to
maintain a 50% duty cycle for any divide ratio.
The following register addresses contain the P divider settings:
• PLL_0, P0 divider: Register 0x0424[3:0]
• PLL_1, P1 divider: Register 0x0524[3:0]
Channel Dividers
The channel divider blocks, Q0_A, Q0_B, Q1_B, and Q1_A,
are 10-bit integer dividers with a divide range of 1 to 1024.
The channel divider block contains duty cycle correction that
guarantees 50% duty cycle for both even and odd divide ratios.
The maximum input frequency to the channel dividers is
1.25 GHz.
The channel dividers are at the following register addresses:
• Q0_A divider: Register 0x0428 to Register 0x042A
• Q0_B divider: Register 0x042C to Register 0x042E
• Q1_A divider: Register 0x0528 to Register 0x052A
• Q1_B divider: Register 0x052C to Register 0x052E
OUTPUT ENABLE
Each of the output channels offers independent control of enable/
disable functionality via the distribution enable register. The
distribution outputs use synchronization logic to control
enable/disable activity to avoid the production of runt pulses
and to ensure that outputs with the same divide ratios become
active/inactive in unison.
OUTPUT MODE AND POWER-DOWN
The output drivers can be individually powered down. The
output mode control (including power-down) can be found
at the following register addresses:
• OUT0A: Register 0x0427[6:4]
• OUT0B: Register 0x042B[7:4]
• OUT1A: Register 0x0527[6:4]
• OUT1B: Register 0x052B[7:4]
The operating mode control includes
• Logic type and pin function
• Output drive strength
• Output polarity
• Divide ratio
• Phase of each output channel
OUT0B and OUT1B provide the 3.3 V CMOS, 1.8 V CMOS,
LVDS, and HSTL modes.
OUT0A and OUT1A provide the 1.8 V CMOS, LVDS, and
HSTL modes.
10644-139
FROM VCO_0
(2940MHz TO 3543MHz)
CHIP RESET
SYNC
10-BIT INTEGER
262kHz TO 1.25GHz
CHANNEL
SYNC
BLOCK
MAX
1.25GHz
MAX
1.25GHz
CHANNEL SYNC
(TO Q0
_
A AND Q0
_
B)
OUT0A
OUT0A
OUT0B
OUT0B
P0
DIVIDER
10-BIT INTEGER
÷Q0
_A
÷Q0_
B
FROM VCO_1
(3405MHz TO 4260MHz)
CHIP RESET
SYNC
10-BIT INTEGER
302kHz TO 1.25GHz
10-BIT INTEGER
CHANNEL
SYNC
BLOCK
MAX
1.25GHz
MAX
1.25GHz
CHANNEL SYNC
(TO Q1_A AND Q1_B)
OUT1A
OUT1A
OUT1B
OUT1B
10644-141
÷Q1_A
÷Q1_B