Datasheet

Data Sheet AD9559
Rev. C | Page 35 of 120
Programmable Digital Loop Filter
The AD9559 loop filter is a third-order digital IIR filter that is
analogous to the third order analog filter shown in Figure 37.
Figure 37. Third Order Analog Loop Filter
The AD9559 has default loop filter coefficients for two DPLL
settings: nominal (70°) phase margin, and high (88.5°) phase
margin. The high phase margin setting is intended for applications
that require <0.1 dB of closed-loop peaking. While these settings
do not normally need to be changed, the user can contact Analog
Devices, Inc. for a tool to calculate new coefficients to tailor the
loop filter to specific requirements.
The AD9559 loop filter block features a simplified architecture
in which the user enters the desired loop characteristics (such
as loop bandwidth) directly into the DPLL registers. This
architecture makes the calculation of individual coefficients
unnecessary in most cases, while still offering complete
flexibility.
To change a digital loop filter coefficient on a profile that is cur-
rently in use, the user must momentarily break the loop for the
new setting to take effect. The user can do this by selecting free
run or holdover mode, or by invalidating (and then revalidating)
the reference input.
DPLL Digitally Controlled Oscillator Free Run Frequency
The AD9559 uses a Σ-Δ modulator as a digitally controlled
oscillator (DCO). The DCO free run frequency can be calculated
from the following equation:
30
_
2
0
8
2
FTW
ff
SYSfreerundco
+
×=
where FTW0 is the value in Register 0x0400 to Register 0x0403
for DPLL_0 (or Register 0x0500 to Register 0x0503 for DPLL_1),
and f
SYS
is the system clock frequency. See the System Clock
section for information on calculating the system clock frequency.
Adaptive Clocking
The AD9559 can support adaptive clocking applications such as
asynchronous mapping and demapping. For these applications,
the output frequency can be dynamically adjusted by up to
±100 ppm from the nominal output frequency without manually
breaking the DPLL loop and reprogramming the part.
The following registers are used in this function:
• Register 0x0444 to Register 0x0446 (DPLL N0 divider)
• Register 0x0447 to Register 0x0449 (DPLL FRAC0 divider)
• Register 0x044A to Register 0x044C (DPLL MOD0 divider)
Note that the register values shown are for REFA/DPLL_0.
There are corresponding registers for all reference input and
DPLL combinations.
Writing to these registers requires an IO_UPDATE by writing
0x01 to Register 0x0005 before the new values take effect.
To make small adjustments to the output frequency, the user
can vary the FRAC (FRAC0 or FRAC1) and issue an IO_UPDATE.
The advantage to using only FRAC to adjust the output frequency
is that the DPLL does not briefly enter holdover. Therefore,
the FRAC bit can be updated as quickly as the phase detector
frequency of the DPLL.
Writing to the N (N0 or N1) and MOD (M0 or M1) dividers allows
for larger changes to the output frequency. When the AD9559
detects a change in the N or MOD value, it automatically enters
and exits holdover for a brief instant without any disturbance in
the output frequency. This limits how quickly the output frequency
can be adapted.
It is important to note that the amount of frequency adjustment
is limited to ±100 ppm before the output PLL (APLL) needs a
recalibration. Variations larger than ±100 ppm are possible, but
such variations may compromise the ability of the AD9559 to
maintain lock over temperature extremes.
It is also important to remember that the rate of change in
output frequency depends on the DPLL loop bandwidth.
DPLL Phase Lock Detector
The DPLL contains an all-digital phase lock detector. The user
controls the threshold sensitivity and hysteresis of the phase
detector via the profile registers.
The phase lock detector behaves in a manner analogous to water in
a tub (see Figure 38). The total capacity of the tub is 4096 units,
with −2048 denoting empty, 0 denoting the 50% point, and +2048
denoting full. The tub also has a safeguard to prevent overflow.
Furthermore, the tub has a low water mark at −1024 and a high
water mark at +1024. To change the water level, the user adds
water with a fill bucket or removes water with a drain bucket.
The user specifies the size of the fill and drain buckets via the
8-bit fill rate and drain rate values in the profile registers.
Figure 38. Lock Detector Diagram
The water level in the tub is what the lock detector uses to
determine the lock and unlock conditions. When the water level
is below the low water mark (−1024), the detector indicates an
unlock condition. Conversely, when the water level is above the
high water mark (+1024), the detector indicates a lock condition.
When the water level is between the marks, the detector holds
its last condition. This concept appears graphically in Figure 38,
with an overlay of an example of the instantaneous water level
(vertical) vs. time (horizontal) and the resulting lock/unlock states.
C
3
C
2
C
1
R
2
R
3
10644-015
0
2048
–2048
1024
–1024
LOCK LEVEL
UNLOCK LEVEL
LOCKED UNLOCKED
PREVIOUS
STATE
FILL
RATE
DRAIN
RATE
10644-017