Datasheet

AD9559 Data Sheet
Rev. C | Page 32 of 120
REFERENCE INPUT PHYSICAL CONNECTIONS
Four pairs of pins (REFA,
REFA
through REFD,
REFD
) provide
access to the reference clock receivers. To accommodate input
signals with slow rising and falling edges, both the differential
and single-ended input receivers employ hysteresis. Hysteresis
also ensures that a disconnected or floating input does not
cause the receiver to oscillate.
When configured for differential operation, the input receivers
accommodate either ac- or dc-coupled input signals. The input
receivers are capable of accepting dc-coupled LVDS and 2.5 V
and 3.3 V LVPECL signals. The receiver is internally dc biased
to handle ac-coupled operation, but there is no internal 50 Ω or
100 Ω termination.
When configured for single-ended operation, the input
receivers exhibit a pull-down load of 47 kΩ (typical). Three
user-programmable threshold voltage ranges are available for
each single-ended receiver. See Register 0x0300 to Register
0x037A for the settings for the reference inputs.
REFERENCE MONITORS
The accuracy of the input reference monitors depends on
a known and accurate system clock period. Therefore, the
functioning of the reference monitors is not operable until the
system clock is stable.
Reference Period Monitor
Each reference input has a dedicated monitor that repeatedly
measures the reference period. The AD9559 uses the reference
period measurements to determine the validity of the reference
based on a set of user-provided parameters in the reference input
area of the register map. See Register 0x0304 through Register
0x030E for the settings for Reference A. There are corresponding
registers for Reference B, C, and D.
The monitor works by comparing the measured period of
a particular reference input with the parameters stored in the
profile register assigned to that same reference input. The
parameters include the reference period, an inner tolerance, and
an outer tolerance. A 40-bit number defines the reference period
in units of femtoseconds (fs). The 40-bit range allows for a
reference period entry of up to 1.1 ms. A 20-bit number defines
the inner and outer tolerances. The value stored in the register
is the reciprocal of the tolerance specification. For example,
a tolerance specification of 50 ppm yields a register value of
1/(50 ppm) = 1/0.000050 = 20,000 (0x04E20).
The use of two tolerance values provides hysteresis for the monitor
decision logic. The inner tolerance applies to a previously faulted
reference and specifies the largest period tolerance that a previously
faulted reference can exhibit before it qualifies as unfaulted. The
outer tolerance applies to an already unfaulted reference. It specifies
the largest period tolerance that an unfaulted reference can
exhibit before being faulted.
To produce decision hysteresis, the inner tolerance must be less
than the outer tolerance. That is, a faulted reference must meet
tighter requirements to become unfaulted than an unfaulted
reference must meet to become faulted.
Reference Validation Timer
Each reference input has a dedicated validation timer. The
validation timer establishes the amount of time that a previously
faulted reference must remain unfaulted before the AD9559
declares that it is valid. The timeout period of the validation
timer is programmable via a 16-bit register (Address 0x030F
and Address 0x0310 for Reference A). The 16-bit number stored
in the validation register represents units of milliseconds (ms),
which yields a maximum timeout period of 65,535 ms.
It is possible to disable the validation timer by programming the
validation timer to 0. With the validation timer disabled, the user
must validate a reference manually via the manual reference
validation override controls register (Address 0x0A02).
Reference Validation Override Control
The user can also override the reference validation logic, and
can either force an invalid reference to be treated as valid, or
force a valid reference to be treated as an invalid reference.
These controls are in Register 0x0A02 to Register 0x0A03.
REFERENCE INPUT BLOCK
Unlike the AD9557, the AD9559 separates the DPLL reference
dividers from the feedback dividers.
The reference input block includes the input receiver, the reference
divider (R divider), and the reference input frequency monitor
for each reference input. The reference input settings are grouped
together in Register 0x0300 to Register 0x037A.
These registers include the following settings:
• Reference logic type (such as differential, single-ended)
• Reference divider (20-bit R divider value)
• Reference input period and tolerance
• Reference validation timer
• Phase and frequency lock detector settings
The reference prescaler reduces the frequency of this signal by
an integer factor, R + 1, where R is the 20-bit value stored in the
appropriate profile register and 0 ≤ R ≤ 1,048,575. Therefore, the
frequency at the output of the R divider (or the input to the
time-to-digital converter, TDC) is as follows:
1+
=
R
f
f
R
TDC
After the R divider, the signal passes to a 4:2 crosspoint that
allows any reference input signal to go to either DPLL.
Each DPLL on the AD9559 has an independent set of feedback
dividers for each reference input, and a description of these
settings can be found in the Digital PLL (DPLL) Core section.