Datasheet

Data Sheet AD9559
Rev. C | Page 31 of 121
THEORY OF OPERATION
Figure 34. Detailed Block Diagram
OVERVIEW
The AD9559 provides clocking outputs that are directly related
in phase and frequency to the selected (active) reference but
with jitter characteristics governed by the system clock, the
digitally controlled oscillator (DCO), and the analog output
PLL (APLL). The AD9559 can be thought of as two copies of
the AD9557 inside one package, with a 4:2 crosspoint controlling
the reference inputs. The AD9559 supports up to four reference
inputs and input frequencies ranging from 2 kHz to 1250 MHz.
The cores of this product are two digital phase-locked loops
(DPLLs). Each DPLL has a programmable digital loop filter that
greatly reduces jitter transferred from the active reference to the
output, and these two DPLLs operate completely independently
of each other. The AD9559 supports both manual and automatic
holdover. While in holdover, the AD9559 continues to provide
an output as long as the system clock is present. The holdover
output frequency is a time average of the output frequency history
just prior to the transition to the holdover condition. The device
offers manual and automatic reference switchover capability if
the active reference is degraded or fails completely. The AD9559
also has adaptive clocking capability that allows the user to
dynamically change the DPLL divide ratios while the DPLLs
are locked.
The AD9559 includes a system clock multiplier, two DPLLs,
and two APLLs. The input signal goes first to the DPLL, which
performs the jitter cleaning and most of the frequency translation.
Each DPLL features a 30-bit digitally controlled oscillator (DCO)
output that generates a signal in the range of 175 MHz to 200 MHz.
The DCO output goes to the APLL, which multiplies the signal
up to a range of 2.9 GHz to 4.2 GHz. That signal is then sent to
the clock distribution section, which has a divide-by-3 to
divide-by-11 P divider cascaded with 10-bit integer channel
dividers (divide-by-1 to divide-by-1024).
The XOA and XOB inputs provide the input for the system clock.
These bits accept a reference clock in the 10 MHz to 600 MHz
range or a 10 MHz to 50 MHz crystal connected directly across
the XOA and XOB inputs. The system clock provides the clocks
to the frequency monitors, the DPLLs, and internal switching logic.
Each APLL on the AD9559 has two differential output drivers.
Each of the four output drivers has a dedicated 10-bit program-
mable post divider. Each differential driver is programmable as
either a single differential or dual single-ended CMOS output.
The clock distribution section operates at up to 1250 MHz.
In differential mode, the output drivers run on a 1.8 V power
supply to offer very high performance with minimal power
consumption. There are two differential modes: LVDS and 1.8 V
HSTL. In 1.8 V HSTL mode, the voltage swing is compatible
with LVPECL. If LVPECL signal levels are required, the designer
can ac-couple the AD9559 output and use Thevenin-equivalent
termination at the destination to drive LVPECL inputs.
In single-ended mode, each differential output driver can operate
as two single-ended CMOS outputs. OUT0A,
OUT0A
and
OUT1A,
OUT1A
support only 1.8 V CMOS operation.
OUT0B,
OUT0B
and OUT1B,
OUT1B
support either 1.8 V or
3.3 V CMOS operation.
XOA
XOB
REFA
REFA
A
REFB
REFB
B
REFC
REFC
C
REFD
REFD
D
÷2
÷2, ÷4, ÷8
×2
÷R
A
÷2
÷R
B
÷2
÷R
C
÷2
÷R
D
REFERENCE
MONITORS
AND
CROSSPOINT
MUX
SYSCLK
MULTIPLIER
REF
OR
XTAL
SYSTEM
CLOCK
DPFD
LOOP
FILTER
TW
CLAMP
NCO_0
FRAC0 ÷ MOD0
÷N0 ÷M0 ÷P0 (÷3 TO ÷11)
PFD/CP
LF
FREE RUN
TUNING WORD
VCO_0
2940MHz TO 3543MHz
÷Q0_A
OUT0A
OUT0A
÷Q0_B
OUT0B
OUT0B
262kHz TO
1.25GHz
÷Q1_A
DPFD
LOOP
FILTER
TW
CLAMP
NCO_1
FRAC1 ÷ MOD1
÷N1 ÷M1
÷P1 (÷3 TO ÷11)
PFD/CP
LF
FREE RUN
TUNING WORD
VCO_1
3405MHz TO 4260MHz
÷Q1_B
OUT1A
OUT1A
OUT1B
OUT1B
302kHz TO
1.25GHz
RESET
SCLK/SCL
SDIO/SDA
M5/CS
M4/SDO
M3 M2 M1 M0
CONTROL INTERFACE/LOGIC
AND EEPROM
INPUT REFERENCE FREQUENCY RANGE:
2kHz TO 1.25GHz
10644-035