Datasheet

AD9559 Data Sheet
Rev. C | Page 30 of 120
APLL VCO Calibration
VCO calibration ensures that, at the time of calibration, the dc
control voltage of the APLL VCO is centered in the middle of its
operating range. The user can calibrate VCO_0 independently of
VCO_1, and vice versa. It is important to remember the following
conditions when calibrating the APLL VCO:
• The system clock must be stable.
• The APLL VCO must have the correct frequency from the
30-bit DCO (digitally controlled oscillator) during
calibration. The free running tuning word is found in
DPLL_0: Registers 0x0400 to 0x0403
DPLL_1: Registers 0x0500 to 0x0503
• The APLL VCO must be recalibrated any time the APLL
frequency changes.
• APLL VCO calibration occurs on the low-to-high
transition of the APLL VCO calibration bit.
APLL_0: Register 0x0A20[1]
APLL_1: Register 0x0A40[1]
• The VCO calibration bit is not an autoclearing bit.
Therefore, this bit must be cleared (and an IO_UPDATE
issued) before the APLL is recalibrated.
• The best way to monitor successful APLL calibration is
by monitoring the APLL locked bit, in the following registers:
APLL_0: Register 0x0D20[3]
APLL_1: Register 0x0D40[3]
Generate the Output Clock
If Register 0x0425 (for PLL_0) and/or Register 0x0525 (for PLL_1)
is programmed for automatic clock distribution synchronization
via the DPLL phase or frequency lock, the synthesized output
signal appears at the clock distribution outputs. Otherwise, set
and then clear the soft sync bit (Bit 2 in Register 0x0A20 for
APLL_0 and Register 0x0A40 for APPL_1) or use a multifunction
pin input (if programmed accordingly) to generate a clock
distribution sync pulse, which causes the synthesized output
signal to appear at the clock distribution outputs.
Generate the Reference Acquisition
After the registers are programmed, clear the user free run bit
(Bit 0 in Register 0x0A22 for DPLL_0 and Register 0x0A42 for
DPPL_1) and issue an IO_UPDATE using Register 0x0005[0] to
invoke all of the register settings programmed up to this point.
The DPLLs lock to the first available reference that has the
highest priority.