Datasheet

Data Sheet AD9559
Rev. C | Page 3 of 120
System Clock (Register 0x0200 to Register 0x0207) .............. 76
Reference Input A (Register 0x0300 to Register 0x031A) ..... 77
Reference Input B (Register 0x0320 to Register 0x033A)...... 78
Reference Input C (Register 0x0340 to Register 0x035A) ..... 79
Reference Input D (Register 0x0360 to Register 0x037A) ..... 81
DPLL_0 Controls (Register 0x0400 to Register 0x0415) ....... 82
APLL_0 Configuration (Register 0x0420 to Register 0x0423) .. 84
PLL_0 Output Sync and Clock Distribution (Register 0x0424
to Register 0x042E) ..................................................................... 85
DPLL_0 Settings for Reference Input A (REFA) (Register
0x0440 to Register 0x044C) ....................................................... 87
DPLL_0 Settings for Reference Input B (REFB) (Register
0x044D to Register 0x0459) ....................................................... 88
DPLL_0 Settings for Reference Input C (REFC) (Register
0x045A to Register 0x0466) ....................................................... 89
DPLL_0 Settings for Reference Input D (REFD) (Register
0x0467 to Register 0x0473) ........................................................ 90
DPLL_1 Controls (Register 0x0500 to Register 0x0515) ....... 91
APLL_1 Configuration (Register 0x0520 to Register 0x0523) ... 93
PLL_1 Output Sync and Clock Distribution (Register 0x0524
to Register 0x052E) ..................................................................... 94
DPLL_1 Settings for Reference Input C (REFC) (Register
0x0540 to Register 0x054C) ....................................................... 96
DPLL_1 Settings for Reference Input D (REFD) (Register
0x054D to Register 0x0559) ....................................................... 97
DPLL_1 Settings for Reference Input A (REFA) (Register
0x055A to Register 0x0566) ....................................................... 98
DPLL_1 Settings for Reference Input B (REFB) (Register
0x0567 to Register 0x0573) ........................................................ 99
Digital Loop Filter Coefficients (Register 0x0800 to Register
0x0817) ....................................................................................... 100
Common Operational Controls (Register 0x0A00 to Register
0x0A0E) ...................................................................................... 101
PLL_0 Operational Controls (Register 0x0A20 to Register
0x0A24) ...................................................................................... 104
PLL_1 Operational Controls (Register 0x0A40 to Register
0x0A44) ...................................................................................... 106
Status ReadBack (Register 0x0D00 to Register 0x0D05) ..... 107
IRQ Monitor (Register 0x0D08 to Register 0x0D10) .......... 108
PLL_0 Read-Only Status (Register 0x0D20 to Register
0x0D2A) ..................................................................................... 110
PLL_1 Read-Only Status (Register 0x0D40 to Register
0x0D4A) ..................................................................................... 112
EEPROM Control (Register 0x0E00 to Register 0x0E03) ... 113
EEPROM Storage Sequence (Register 0x0E10 to Register
0x0E3C) ...................................................................................... 113
Outline Dimensions ...................................................................... 120
Ordering Guide ......................................................................... 120
REVISION HISTORY
5/13—Rev. B to Rev. C
Changes to Table 25 ........................................................................ 49
3/13—Rev. A to Rev. B
Changes to Device Register Programming Using a Register
Setup File Section ............................................................................ 27
Changed 101100 to 1101100, Table 25 ......................................... 49
12/12—Rev. 0 to Rev. A
Change to Features Section .............................................................. 1
Changes to DPLL Overview Section, Figure 35, and
Figure 36 ........................................................................................... 34
Changes to EEPROM Upload Section and Manual EEPROM
Download Section ........................................................................... 45
Changes to Table 25 ........................................................................ 49
Changes to Table 34 ........................................................................ 63
Changes to Table 91 ........................................................................ 87
Changes to Table 92, Table 96, and Table 97 ............................... 88
Changes to Table 101 and Table 102 ............................................. 89
Changes to Table 106 and Table 107 ............................................. 90
Changes to Table 126 ...................................................................... 97
Changes to Table 127, Table 131, and Table 132 ......................... 97
Changes to Table 136 and Table 137 ............................................. 98
Changes to Table 141 and Table 142 ............................................. 99
Changes to Table 179 .................................................................... 113
Updated Outline Dimensions...................................................... 120
7/12—Revision 0: Initial Version