Datasheet

Data Sheet AD9559
Rev. C | Page 29 of 120
Other reference input settings can be found at the following
register addresses:
• Reference input enable information is found in the DPLL
Feedback Dividers section.
• Reference power-down is found in Register 0x0A01.
• Reference priority settings are found in the DPLL profiles.
DPLL_0: Registers 0x0440 through 0x0473
DPLL_1: Registers 0x0540 through 0x0573
• Reference switching mode settings are found in
DPLL_0: Register 0x0A22
DPLL_1: Register 0x0A42
DPLL Controls and Settings
The DPLL control parameters are separate for DPLL_0 and
DPLL_1. They reside in the following locations:
• DPLL_0: Register 0x0400 to Register 0x0415
• DPLL_1: Register 0x0500 to Register 0x0515
These registers include the following settings:
• 30-bit free running frequency
• DPLL pull-in range limits
• DPLL closed-loop phase offset
• Tuning word history control (for holdover operation)
• Phase slew control (for controlling the phase slew rate
during a closed-loop phase adjustment)
With the exception of the free running tuning word, the default
values of these registers are fine for normal operation. The free
running frequency of the DPLL determines the frequency that
appears at the APLL input when user free run mode is selected.
The correct free running frequency is required for the APLL to
calibrate and lock correctly.
Note that the user free run bits, which enable user free run mode,
can be found in the following registers:
• DPLL_0: Register 0x0A22 = 0x01
• DPLL_1: Register 0x0A42 = 0x01
Output PLLs (APLLs) and Output Drivers
The registers controlling the APLLs and output drivers reside at
the following locations:
• APLL_0: Register 0x0420 to Register 0x042E
• APLL_1: Register 0x0520 to Register 0x052E
The following functions are controlled in these registers:
• APLL settings (feedback divider, charge pump current)
• Output synchronization mode
• Output divider values
• Output enable/disable (disabled by default)
• Output logic type
Note that the APLL calibration and synchronization bits can be
found in the following registers:
• APLL_0: Register 0x0A20
• APLL_1: Register 0x0A40
DPLL Feedback Dividers
Each digital PLL has separate feedback divider settings for each
reference input. This allows the user to have each digital PLL
perform a different frequency translation. However, there is
only one reference divider (R divider) for each reference input.
The feedback divider register settings reside in the following
locations:
• DPLL_0, REFA: Register 0x0440 to Register 0x044C
• DPLL_0, REFB: Register 0x044D to Register 0x0459
• DPLL_0, REFC: Register 0x045A to Register 0x0466
• DPLL_0, REFD: Register 0x0467 to Register 0x0473
• DPLL_1, REFC: Register 0x0540 to Register 0x054C
• DPLL_1, REFD: Register 0x054D to Register 0x0559
• DPLL_1, REFA: Register 0x055A to Register 0x0566
• DPLL_1, REFB: Register 0x0567 to Register 0x0573
These registers include the following settings:
• Reference priority
• Reference input enable (separate for each DPLL)
• DPLL loop bandwidth
• DPLL loop filter
• DPLL feedback divider (integer portion)
• DPLL feedback divider (fractional portion)
Common Operational Controls
The common operational controls reside at Register 0x0A00 to
Register 0x0A0E and include the following:
• Simultaneous calibration and synchronization of both PLLs
• Global power-down
• Reference power-down
• Reference validation override
• IRQ clearing (for all IRQs)
PLL_0 and PLL_1 Operational Controls
The PLL_0 and PLL_1 operational controls are located at
Register 0x0A20 to Register 0x0A44 and include the following:
• APLL calibration and synchronization
• Output driver enable and power-down
• DPLL reference input switching modes
• DPLL phase offset control