Datasheet

Data Sheet AD9559
Rev. C | Page 27 of 120
GETTING STARTED
CHIP POWER MONITOR AND STARTUP
The AD9559 monitors the voltage on the power supplies at
power-up. When VDD3 is greater than 2.35 V ± 0.1 V and
VDD is greater than 1.4 V ± 0.05 V, the device generates a
20 ms reset pulse. The power-up reset pulse is internal and
independent of the
RESET
pin. This internal power-up reset
sequence eliminates the need for the user to provide external
power supply sequencing. Within 45 ns after the internal reset
pulse, the M5 to M0 multifunction pins behave as high
impedance digital inputs and continue to do so until
programmed otherwise.
During a device reset (either via the power-up reset pulse or
the
RESET
pin), the M3 to M0 multifunction pins behave as
high impedance inputs; and at the point where the reset
condition is cleared, level-sensitive latches capture the logic
pattern that is present on the multifunction pins.
MULTIFUNCTION PINS AT RESET/POWER-UP
At start-up, the M0 and M1 pins allow the user to either bypass
EEPROM loading or load one of three EEPROM profiles. See
Table 23 for information on setting the M0 and M1 pins.
Pin M3 selects SPI or I²C mode: SPI mode is set by pulling M3
low at startup. If M3 is high, I²C mode is set, and the M4 and
M5 pins determine the I²C address. See Table 25 for information
on SPI/I²C configuration.
If 4-wire SPI mode is selected, by setting Bit 7 of Register 0x0000,
the M4/SDO pin functions as SDO and is not available for other
functions as an M pin. However, in I²C mode and in 3-wire SPI
mode, M4 is available as the fifth M pin.
A sixth M pin, M5, is available if the serial port is in I²C mode
or 2-wire SPI mode. In 2-wire SPI mode, there is no
CS
pin
available, and it is assumed that the AD9559 is the only device
on the SPI bus.
DEVICE REGISTER PROGRAMMING USING
A REGISTER SETUP FILE
The evaluation software contains a programming wizard and
a convenient graphical user interface that assists the user in
determining the optimal configuration for the DPLLs, APLLs,
and SYSCLK based on the desired input and output frequencies.
It generates a register setup file with a .STP extension that is
easily readable using a text editor.
The user can configure PLL_0 and PLL_1 independently. To do
so, the user should program the common registers (such as the
system clock and reference inputs) first. Next, the registers that
are unique to PLL_0 or PLL_1 can be configured
independently.
After using the evaluation software to create the setup file, use
the following sequence to program the AD9559:
1. Set user free run mode.
DPLL_0: Register 0x0A22 = 0x01.
DPLL_1: Register 0x0A42 = 0x01.
2. Update all registers (also referred to as IO_UPDATE).
Register 0x0005 = 0x01.
3. Write the register values in the STP file from Address 0x0000
to Address 0x0207.
4. IO_UPDATE. Register 0x0005 = 0x01.
5. Verify that SYSCLK is stable. Register 0x0D01[1] = 1.
The user must issue an IO_UPDATE each time before
polling Register 0x0D01.
6. For the outputs to toggle prior to DPLL phase or frequency
lock, set the following:
APLL_0: Register 0x0A20 = 0x04 (soft sync).
APLL_1: Register 0x0A40 = 0x04 (soft sync).
IO_UPDATE. Register 0x0005 = 0x01.
7. Write the rest of the registers in the STP file starting at
Address 0x0300.
8. Calibrate APLL on next IO_UPDATE.
APLL_0: Register 0x0A20 = 0x02.
APLL_1: Register 0x0A40 = 0x02.
9. IO_UPDATE. Register 0x0005 = 0x01.
10. Clear user free run mode.
DPLL_0: Register 0x0A22[0] = 0b.
DPLL_1: Register 0x0A42[0] = 0b.
11. IO_UPDATE. Register 0x0005 = 0x01.