Datasheet

AD9559 Data Sheet
Rev. C | Page 118 of 120
Table 196. Multifunction Pin Output Functions (D7 = 1)
Bits[D7:D0] Value Output Function Source Proxy
0x80 Static Logic 0 None
0x81 Static Logic 1 None
0x82 System clock divided by 32 None
0x83 Watchdog timer output (40 ns strobe when timer expires) None
0x84 EEPROM upload (write to EEPROM) in progress Register 0x0D00, Bit 0
0x85 EEPROM download (read from EEPROM) in progress Register 0x0D00, Bit 1
0x86 EEPROM fault detected Register 0x0D00, Bit 2
0x88 SYSCLK PLL lock detected Register 0x0D01, Bit 0
0x89 SYSCLK PLL stable Register 0x0D01, Bit 1
0x8A
PLL_0 and PLL_1 all locked (logical AND of 0x8B and 0x8C)
Register 0x0D01, Bit 2 and Bit 3
0x8B (DPLL_0 phase lock) and (APLL_0 lock) and (sys PLL lock) Register 0x0D01, Bit 2
0x8C (DPLL_1 phase lock) and (APLL_1 lock) and (sys PLL lock) Register 0x0D01, Bit 3
0x90 (IRQ_common) OR (IRQ_PLL_0) OR (IRQ_PLL_1) None
0x91 IRQ_common None
0x92 IRQ_PLL_0 None
0x93 IRQ_PLL_1 None
0xA0/0xA1/0xA2/0xA3 REFA/REFB/REFC/REFD fault Register 0x0D02/0x0D03/0x0D04/0x0D05, Bit 2
0xA8/0xA9/0xAA/0xAB REFA/REFB/REFC/REFD valid Register 0x0D02/0x0D03/0x0D04/0x0D05, Bit 3
0xB0 (DPLL_0 REFA active) OR (DPLL_1 REFA active) Register 0x0D02, Bit 4 || Bit 5
0xB1 (DPLL_0 REFB active) OR (DPLL_1 REFB active) Register 0x0D03, Bit 4 || Bit 5
0xB2
(DPLL_0 REFC active) OR (DPLL_1 REFC active)
Register 0x0D04, Bit 4 || Bit 5
0xB3 (DPLL_0 REFD active) OR (DPLL_1 REFD active) Register 0x0D05, Bit 4 || Bit 5
0xC0 DPLL_0 phase locked Register 0x0D20, Bit 1
0xC1 DPLL_0 frequency locked Register 0x0D20, Bit 2
0xC2 APLL_0 lock detect Register 0x0D20, Bit 3
0xC3 APLL_0 cal in process Register 0x0D20, Bit 4
0xC4
DPLL_0 active
Register 0x0D0C, Bit 4 || Bit 3 || Bit 2 || Bit 1
0xC5 DPLL_0 in free run mode Register 0x0D21, Bit 0
0xC6 DPLL_0 in holdover Register 0x0D21, Bit 1
0xC7 DPLL_0 in reference switchover Register 0x0D21, Bit 2
0xC8 DPLL_0 tuning word history available Register 0x0D22, Bit 0
0xC9 DPLL_0 tuning word history updated Register 0x0D0C, Bit 4
0xCA DPLL_0 tuning word clamp activated Register 0x0D22, Bit 1
0xCB DPLL_0 phase slew limited Register 0x0D22, Bit 2
0xCC PLL_0 clock distribution sync pulse Register 0x0D0D, Bit 4
0xD0 DPLL_1 phase locked Register 0x0D40, Bit 1
0xD1 DPLL_1 frequency locked Register 0x0D40, Bit 2
0xD2
APLL_1 lock detect
Register 0x0D40, Bit 3
0xD3 APLL_1 cal in process Register 0x0D40, Bit 4
0xD4 DPLL_1 active Register 0x0D0F, Bit 4 || Bit 3 || Bit 2 || Bit 1
0xD5 DPLL_1 in free run mode Register 0x0D41, Bit 0
0xD6 DPLL_1 in holdover Register 0x0D41, Bit 1
0xD7 DPLL_1 in reference switchover Register 0x0D41, Bit 2
0xD8 DPLL_1 tuning word history available Register 0x0D42, Bit 0
0xD9 DPLL_1 tuning word history updated Register 0x0D0F, Bit 4
0xDA DPLL_1 tuning word clamp activated Register 0x0D42, Bit 1
0xDB DPLL_1 phase slew limited Register 0x0D42, Bit 2
0xDC PLL_1 clock distribution sync pulse Register 0x0D10, Bit 4
0xDD to 0xFF Reserved