Datasheet

Data Sheet AD9559
Rev. C | Page 113 of 120
Table 178. DPLL_1 Phase Lock and Frequency Lock Bucket Levels
Address Bits Bit Name Description
0x0D47 [7:0] DPLL_1 phase
lock detect bucket
Read-only DPLL_1 lock detect bucket level, Bits[7:0]; see the DPLL Frequency Lock Detector section.
0x0D48 [7:4] Reserved Reserved.
[3:0] DPLL_1 phase
lock detect bucket
Read-only DPLL_1 lock detect bucket level, Bits[11:8]; see the DPLL Frequency Lock Detector section.
0x0D49 [7:0] Frequency tub Read-only DPLL_1 frequency lock detect bucket level, Bits[7:0]; see the DPLL Phase Lock Detector section.
0x0D4A [7:4] Reserved Reserved.
[3:0] Frequency tub Read-only DPLL_1 frequency lock detect bucket level, Bits[11:8]; see the DPLL Phase Lock Detector section.
EEPROM CONTROL (REGISTER 0x0E00 TO REGISTER 0x0E03)
Table 179. EEPROM Control
Address Bits Bit Name Description
0x0E00 [7:1] Reserved Reserved
0 Write enable EEPROM write enable/protect.
0 (default) = EEPROM write protected
1 = EEPROM write enabled
0x0E01 [7:4] Reserved Reserved
[3:0] Conditional value When set to a nonzero value, it establishes the condition for EEPROM downloads. The default value is 0.
0x0E02 [7:1] Reserved Reserved
0 Save to EEPROM Uploads data to the EEPROM (see the EEPROM Storage Sequence (Register 0x0E10 to Register 0x0E3C)
section for more information). Once an EEPROM save/load transfer is complete, the user should wait
a minimum of 10 µs before starting the next EEPROM save/load transfer.
0x0E03 [7:2] Reserved Reserved
1 Load from EPROM Downloads data from the EEPROM. Once an EEPROM save/load transfer is complete, the user should
wait a minimum of 10 µs before starting the next EEPROM save/load transfer.
0 Reserved Reserved
EEPROM STORAGE SEQUENCE (REGISTER 0x0E10 TO REGISTER 0x0E3C)
The default settings of Register 0x0E10 to Register 0x0E33 contain the default EEPROM instruction sequence. The tables in this section
provide descriptions of the register defaults, assuming that the controller has been instructed to carry out an EEPROM storage sequence
in which all of the registers are stored and loaded by the EEPROM.
Table 180. EEPROM Storage Sequence for M Pin Settings and IRQ Masks
Address Bits Bit Name Description
0x0E10 [7:0] User free run The default value of this register is 0x98, which the controller interprets as a user free run command for
both PLLs. The controller stores 0x98 in the EEPROM and increments the EEPROM address pointer.
0x0E11 [7:0] User scratchpad The default value of this register is 0x01, which is a data instruction. Its decimal value is 1, which tells
the controller to transfer two bytes of data (1 + 1), beginning at the address specified by the next two
bytes. The controller stores 0x01 in the EEPROM and increments the EEPROM address pointer.
0x0E12 [7:0] The default value of these two registers is 0x000E. Because the previous register contains a data
instruction, these two registers define a starting address (in this case, 0x000E). The controller stores
0x000E in the EEPROM and increments the EEPROM pointer by 2. It then transfers two bytes from the
register map (beginning at Address 0x000E) to the EEPROM and increments the EEPROM address
pointer by 3 (two data bytes and one checksum byte). The two bytes transferred correspond to the
user scratchpad in the register map.
0x0E13
0x0E14 [7:0] M pins and IRQ
masks
The default value of this register is 0x12, which the controller interprets as a data instruction. Its decimal
value is 18, which tells the controller to transfer 19 bytes of data (18 + 1), beginning at the address
specified by the next two bytes. The controller stores 0x12 in the EEPROM and increments the
EEPROM address pointer.
0x0E15 [7:0] The default value of these two registers is 0x0100. Because the previous register contains a data
instruction, these two registers define a starting address (in this case, 0x0100). The controller stores
0x0100 in the EEPROM and increments the EEPROM pointer by 2. It then transfers 19 bytes from the
register map (beginning at Address 0x0100) to the EEPROM and increments the EEPROM address
pointer by 20 (19 data bytes and one checksum byte). The 19 bytes transferred correspond to the
M pin and IRQ settings in the register map.
0x0E16