Datasheet

AD9559 Data Sheet
Rev. C | Page 110 of 120
Table 170. IRQ Monitor for Digital PLL1 (DPLL_1)
Address Bits Bit Name Description
0x0D0E 7 Frequency unclamped IRQ indicating that DPLL_1 has exited a frequency clamped state
6
Frequency clamped
IRQ indicating that DPLL_1 has entered a frequency clamped state
5 Phase slew unlimited IRQ indicating that DPLL_1 has exited a phase slew limited state
4 Phase slew limited IRQ indicating that DPLL_1 has entered a phase slew limited state
3 Frequency unlocked IRQ indicating that DPLL_1 has lost frequency lock
2 Frequency locked IRQ indicating that DPLL_1 has acquired frequency lock
1 Phase unlocked IRQ indicating that DPLL_1 has lost phase lock
0 Phase locked IRQ indicating that DPLL_1 has acquired phase lock
0x0D0F 7 DPLL_1 switching IRQ indicating that DPLL_1 is switching to a new reference
6 DPLL_1 free run IRQ indicating that DPLL_1 has entered free run mode
5 DPLL_1 holdover IRQ indicating that DPLL_1 has entered holdover mode
4
History updated
IRQ indicating that DPLL_1 has updated its tuning word history
3 REFD activated IRQ indicating that DPLL_1 has activated REFD
2 REFC activated IRQ indicating that DPLL_1 has activated REFC
1 REFB activated IRQ indicating that DPLL_1 has activated REFB
0 REFA activated IRQ indicating that DPLL_1 has activated REFA
0x0D10 [7:5] Reserved Reserved
4 Sync distribution IRQ indicating a distribution sync event
3 APLL_1 unlocked IRQ indicating that APLL_1 has been unlocked
2 APLL_1 locked IRQ indicating that APLL_1 has been locked
1
APLL_1 cal ended
IRQ indicating that APLL_1 calibration complete
0 APLL_1 cal started IRQ indicating that APLL_1 calibration started
PLL_0 READ-ONLY STATUS (REGISTER 0x0D20 TO REGISTER 0x0D2A)
All bits in Register 0x0D20 to Register 0x0D2A are read only. To report the latest status, these bits require an IO_UPDATE (Register 0x0005 =
0x01) immediately before being read.
Table 171. PLL_0 Lock Status
Address Bits Bit Name Description
0x0D20 [7:5] Reserved Default: 000b
4 APLL_0
cal in progress
The control logic holds this bit set while the calibration of the APLL_0 VCO is in
progress.
3 APLL_0 locked Indicates the status of APLL_0.
0 = unlocked.
1 = locked.
2 DPLL_0
frequency lock
Indicates the frequency lock status of DPLL_0.
0 = unlocked.
1 = locked.
1 DPLL_0
phase lock
Indicates the phase lock status of DPLL_0.
0 = unlocked.
1 = locked.
0 PLL_0 all locked Indicates the status of the system clock, APLL_0, and DPLL_0.
0 = system clock PLL or APLL_0 or DPLL_0 is unlocked.
1 = all three PLLs (system clock PLL, APLL_0, and DPLL_0) are locked.