Datasheet

AD9559 Data Sheet
Rev. C | Page 108 of 120
Table 167. Status of Reference Inputs
Address Bits Bit Name Description
0x0D02 [7:6] Reserved Default: 00b.
5
DPLL_1 REFA active
This bit is 1 if DPLL_1 is either locked to or attempting to lock to REFA.
4 DPLL_0 REFA active This bit is 1 if DPLL_0 is either locked to or attempting to lock to REFA.
3 REFA valid This bit is 1 if the REFA frequency is within the programmed limits.
2 REFA fault This bit is 1 if the REFA frequency is outside of the programmed limits.
1 REFA fast This bit is 1 if the REFA frequency is higher than allowed by its profile settings.
0 REFA slow This bit is 1 if the REFA frequency is lower than allowed by its profile settings.
0x0D03 [7:6] Reserved Default: 00b.
5 DPLL_1 REFB active This bit is 1 if DPLL_1 is either locked to or attempting to lock to REFB.
4 DPLL_0 REFB active This bit is 1 if DPLL_0 is either locked to or attempting to lock to REFB.
3 REFB valid This bit is 1 if the REFB frequency is within the programmed limits.
2
REFB fault
This bit is 1 if the REFB frequency is outside of the programmed limits.
1 REFB fast This bit is 1 if the REFB frequency is higher than allowed by its profile settings.
0 REFB slow This bit is 1 if the REFB frequency is lower than allowed by its profile settings.
0x0D04 [7:6] Reserved Default: 00b.
5 DPLL_1 REFC active This bit is 1 if DPLL_1 is either locked to or attempting to lock to REFC.
4 DPLL_0 REFC active This bit is 1 if DPLL_0 is either locked to or attempting to lock to REFC.
3 REFC valid This bit is 1 if the REFC frequency is within the programmed limits.
2 REFC fault This bit is 1 if the REFC frequency is outside of the programmed limits.
1 REFC fast This bit is 1 if the REFC frequency is higher than allowed by its profile settings.
0
REFC slow
This bit is 1 if the REFC frequency is lower than allowed by its profile settings.
0x0D05 [7:6] Reserved Default: 00b.
5 DPLL_1 REFD active This bit is 1 if DPLL_1 is either locked to or attempting to lock to REFD.
4
DPLL_0 REFD active
This bit is 1 if DPLL_0 is either locked to or attempting to lock to REFD.
3 REFD valid This bit is 1 if the REFD frequency is within the programmed limits.
2 REFD fault This bit is 1 if the REFD frequency is outside of the programmed limits.
1 REFD fast This bit is 1 if the REFD frequency is higher than allowed by its profile settings.
0 REFD slow This bit is 1 if the REFD frequency is lower than allowed by its profile settings.
IRQ MONITOR (REGISTER 0x0D08 TO REGISTER 0x0D10)
If not masked via the IRQ mask registers (Register 0x010A to Register 0x0112), the appropriate IRQ monitor bit is set to Logic 1 when the
indicated event occurs. These bits can be cleared only by a device reset, or by setting the clear all IRQs bit in Register 0x0A05, or by
setting the IRQ clearing registers (Register 0x0A05 to Register 0x0A0E).
Table 168. IRQ for Common Functions
Address Bits Bit Name Description
0x0D08 7 Reserved Reserved
6 SYSCLK unlocked IRQ indicating a SYSCLK PLL state transition from locked to unlocked
5 SYSCLK stable IRQ indicating that SYSCLK stability time has expired and that the SYSCLK PLL is
considered to be stable
4
SYSCLK locked
IRQ indicating a SYSCLK PLL state transition from unlocked to locked
3 Watchdog timer IRQ indicating expiration of the watchdog timer
2 Reserved Reserved
1 EEPROM fault IRQ indicating a fault during an EEPROM load or save operation
0 EEPROM complete IRQ indicating successful completion of an EEPROM load or save operation