Datasheet

Data Sheet AD9559
Rev. C | Page 107 of 120
Table 163. DPLL_1 Reset
Address Bits Bit Name Description
0x0A43 [7:3] Reserved Default: 00000b.
2 Reset DPLL_1
loop filter
Setting this bit clears the digital loop filter (intended as a debug tool).
1 Reset DPLL_1
TW history
Setting this bit resets the tuning word history logic (part of holdover functionality).
0 Reset DPLL_1
autosync
Setting this bit resets the automatic synchronization logic (see Register 0x0525).
Table 164. DPLL_1 Phase
Address Bits Bit Name Description
0x0A44 [7:3] Reserved Default: 00000b.
2 DPLL_1 reset phase
offset
Resets the incremental phase offset to zero.
This is an autoclearing bit.
1 DPLL_1 decrement
phase offset
Decrements the incremental phase offset by the amount specified in the incremental phase
lock offset step size register (Register 0x0512 to Register 0x0513).
This is an autoclearing bit.
0 DPLL_1 increment
phase offset
Increments the incremental phase offset by the amount specified in the incremental phase
lock offset step size register (Register 0x0512 and Register 0x0513).
This is an autoclearing bit.
STATUS READBACK (REGISTER 0x0D00 TO REGISTER 0x0D05)
All bits in Register 0x0D00 to Register 0x0D05 are read only. To report the latest status, these bits require an IO_UPDATE (Register 0x0005 =
0x01) immediately before being read.
Table 165. EEPROM Status
Address Bits Bit Name Description
0x0D00
[7:3]
Reserved
Default: 00000b.
2 Fault detected An error occurred while saving data to or loading data from the EEPROM.
1 Load in progress The control logic sets this bit while data is being read from the EEPROM.
0
Save in progress
The control logic sets this bit while data is being written to the EEPROM.
Table 166. SYSCLK Status
Address Bits Bit Name Description
0x0D01 [7:4] Reserved Default: 0x0.
3 PLL_1 all locked Indicates the status of the system clock, APLL_1, and DPLL_1.
0 = system clock or APLL_1 or DPLL_1 is unlocked.
1 = all three PLLs (system clock, APLL_1, and DPLL_1) are locked.
2 PLL_0 all locked Indicates the status of the system clock, APLL_0, and DPLL_0.
0 = system clock or APLL_0 or DPLL_0 is unlocked.
1 = all three PLLs (system clock, APLL_0, and DPLL_0) are locked.
1 System clock stable The control logic sets this bit when the device considers the system clock to be stable (see the
System Clock Stability Timer section).
0 SYSCLK lock detect Indicates the status of the system clock PLL.
0 = unlocked.
1 = locked.