Datasheet

AD9559 Data Sheet
Rev. C | Page 106 of 120
PLL_1 OPERATIONAL CONTROLS (REGISTER 0x0A40 TO REGISTER 0x0A44)
Table 160. PLL_1 Sync and Calibration
Address Bits Bit Name Description
0x0A40
[7:3]
Reserved
Default: 0x0.
2 APLL_1 soft sync Setting this bit initiates synchronization of the clock distribution output.
Default: 0b.
Nonmasked outputs stall when value is 1; restart is initialized on a 1-to-0 transition.
1 APLL_1 calibrate
(not self-clearing)
1 = initiates VCO calibration (calibration occurs on a 0-to-1 transition).
0 (default) = does nothing.
This bit is not autoclearing.
0 PLL_1 power-down Places DPLL_1, APLL_1, and PLL_1 clock in deep sleep mode.
Default: the device is not powered down.
Table 161. PLL_1 Output Disable
Address Bits Bit Name Description
0x0A41
[7:4]
Reserved
Default 0x0.
3 OUT1B disable Setting this bit puts the only OUT1B driver into power-down. Default: 0b.
Channel synchronization is maintained, but runt pulses may be generated.
2 OUT1A disable Setting this bit puts the only OUT1A driver into power-down. Default: 0b.
Channel synchronization is maintained, but runt pulses may be generated.
1 OUT1B channel
power-down
Setting this bit puts the OUT1B divider and driver into power-down. Default: 0b.
This mode saves the most power, but runt pulses may be generated during exit.
0 OUT1A channel
power-down
Setting this bit puts the OUT1A divider and driver into power-down. Default: 0b.
This mode saves the most power, but runt pulses may be generated during exit.
Table 162. DPLL_1 User Mode
Address Bits Bit Name Description
0x0A42 7 Reserved Default: 0b.
[6:5] DPLL_1
manual reference
Input reference when user selection mode = 00, 01, 10, or 11.
00 (default) = Input Reference A.
01 = Input Reference B.
10 = Input Reference C.
11 = Input Reference D.
[4:2] DPLL_1
switching mode
Selects the operating mode of the reference switching state machine.
Reference Switchover
Mode, Bits[2:0]
Reference Selection Mode
000 Automatic revertive mode
001 Automatic nonrevertive mode
010 Manual reference select mode (with automatic fallback)
011 Manual reference select mode (with automatic holdover fallback)
100 Manual reference select mode (without holdover fallback)
101 Not used
110 Not used
111 Not used
1 DPLL_1
user holdover
This bit forces DPLL_1 into holdover mode.
0 (default) = normal operation.
1 (default) = DPLL_1 is forced into holdover mode until this bit is cleared.
0 DPLL_1
user free run
This bit forces DPLL_1 into free run mode.
0 (default) = normal operation.
1 = DPLL_1 is forced into free run mode until this bit is cleared.