Datasheet

Data Sheet AD9559
Rev. C | Page 105 of 120
Table 157. DPLL_0 User Mode
Address Bits Bit Name Description
0x0A22 7 Reserved Default: 0b
[6:5] DPLL_0
manual reference
Input reference when user selection mode = 00, 01, 10, or 11
00 (default) = Input Reference A
01 = Input Reference B
10 = Input Reference C
11 = Input Reference D
[4:2] DPLL_0
switching mode
Selects the operating mode of the reference switching state machine
Reference Switchover
Mode, Bits[2:0] Reference Selection Mode
000 Automatic revertive mode
001 Automatic nonrevertive mode
010 Manual reference select mode (with automatic fallback)
011 Manual reference select mode (with automatic holdover fallback)
100
Manual reference select mode (without holdover fallback)
101 Not used
110 Not used
111
Not used
1 DPLL_0
user holdover
Forces DPLL_0 into holdover mode
0 (default) = normal operation
1 (default) = DPLL_0 is forced into holdover mode until this bit is cleared
0 DPLL_0
user free run
Forces DPLL_0 into free run mode
0 (default) = normal operation
1 = DPLL_0 is forced into free run mode until this bit is cleared
Table 158. DPLL_0 Reset
Address Bits Bit Name Description
0x0A23 [7:3] Reserved Default: 00000b.
2 Reset DPLL_0
loop filter
Setting this bit clears the digital loop filter (intended as a debug tool).
1 Reset DPLL_0
TW history
Setting this bit resets the tuning word history logic (part of holdover functionality).
0 Reset DPLL_0
autosync
Setting this bit resets the automatic synchronization logic (see Register 0x0425).
Table 159. DPLL_0 Phase
Address Bits Bit Name Description
0x0A24 [7:3] Reserved Default: 00000b.
2 DPLL_0 reset phase
offset
Resets the incremental phase offset to zero.
This is an autoclearing bit.
1 DPLL_0 decrement
phase offset
Decrements the incremental phase offset by the amount specified in the incremental phase
lock offset step size registers (Register 0x0412 and Register 0x0413).
This is an autoclearing bit.
0 DPLL_0 increment
phase offset
Increments the incremental phase offset by the amount specified in the incremental phase
lock offset step size registers (Register 0x0412 and Register 0x0413).
This is an autoclearing bit.