Datasheet

AD9559 Data Sheet
Rev. C | Page 104 of 120
Table 154. IRQ Clearing for Digital PLL1 (DPLL_1)
Address Bits Bit Name Description
0x0A0C 7 Frequency unclamp Clears IRQ indicating that DPLL_1 has exited a frequency clamped state
6
Frequency clamp
Clears IRQ indicating that DPLL_1 has entered a frequency clamped state
5 Phase slew unlimited Clears IRQ indicating that DPLL_1 has exited a phase slew limited state
4 Phase slew limited Clears IRQ indicating that DPLL_1 has entered a phase slew limited state
3 Frequency unlocked Clears IRQ indicating that DPLL_1 has lost frequency lock
2 Frequency locked Clears IRQ indicating that DPLL_1 has acquired frequency lock
1 Phase unlocked Clears IRQ indicating that DPLL_1 has lost phase lock
0 Phase locked Clears IRQ indicating that DPLL_1 has acquired phase lock
0x0A0D 7 DPLL_1 switching Clears IRQ indicating that DPLL_1 is switching to a new reference
6 DPLL_1 free run Clears IRQ indicating that DPLL_1 has entered free run mode
5 DPLL_1 holdover Clears IRQ indicating that DPLL_1 has entered holdover mode
4
History updated
Clears IRQ indicating that DPLL_1 has updated its tuning word history
3 REFD activated Clears IRQ indicating that DPLL_1 has activated REFD
2 REFC activated Clears IRQ indicating that DPLL_1 has activated REFC
1 REFB activated Clears IRQ indicating that DPLL_1 has activated REFB
0 REFA activated Clears IRQ indicating that DPLL_1 has activated REFA
0x0A0E [7:5] Reserved Reserved
4 Sync distribution Clears IRQ indicating a distribution sync event
3 APLL_1 unlocked Clears IRQ indicating that APLL_1 has been unlocked
2 APLL_1 locked Clears IRQ indicating that APLL_1 has been locked
1
APLL_1 cal complete
Clears IRQ indicating that APLL_1 calibration complete
0 APLL_1 cal started Clears IRQ indicating that APLL_1 calibration started
PLL_0 OPERATIONAL CONTROLS (REGISTER 0x0A20 TO REGISTER 0x0A24)
Table 155. PLL_0 Sync and Calibration
Address Bits Bit Name Description
0x0A20 [7:3] Reserved Default: 0x0
2 APLL_0 soft sync Setting this bit initiates synchronization of the clock distribution output. Default: 0b.
Nonmasked outputs stall when value is 1; restart is initialized on a 1-to-0 transition.
1
APLL_0 calibrate
(not self-clearing)
1 = initiates VCO calibration (calibration occurs on a 0-to-1 transition).
0 (default) = does nothing.
This bit is not an autoclearing bit.
0
PLL_0 power-down
Places DPLL_0, APLL_0, and PLL_0 clock in deep sleep mode.
Default: the device is not powered down.
Table 156. PLL_0 Output Disable
Address Bits Bit Name Description
0x0A21 [7:4] Reserved Default 0x0
3 OUT0B disable Setting this bit puts the only OUT0B driver into power-down. Default: 0b.
Channel synchronization is maintained, but runt pulses may be generated.
2 OUT0A disable Setting this bit puts the only OUT0A driver into power-down. Default: 0b.
Channel synchronization is maintained, but runt pulses may be generated.
1 OUT0B channel power-down Setting this bit puts the OUT0B divider and driver into power-down. Default: 0b.
This mode saves the most power, but runt pulses may be generated during exit.
0 OUT0A channel power-down Setting this bit puts the OUT0A divider and driver into power-down. Default: 0b.
This mode saves the most power, but runt pulses may be generated during exit.